Search

Arezoo Sherkat

Examiner (ID: 12013)

Most Active Art Unit
2434
Art Unit(s)
2494, IPBS, 2431, 2131, 2434
Total Applications
370
Issued Applications
274
Pending Applications
15
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9544457 [patent_doc_number] => 20140169104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'NONVOLATILE FLASH MEMORY STRUCTURES INCLUDING FULLERENE MOLECULES AND METHODS FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/138294 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11578 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138294
Nonvolatile flash memory structures including fullerene molecules and methods for manufacturing the same Dec 22, 2013 Issued
Array ( [id] => 9420290 [patent_doc_number] => 20140104940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'INTERNAL VOLTAGE GENERATING CIRCUIT OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/133153 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5563 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133153 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133153
Internal voltage generating circuit of phase change random access memory device and method thereof Dec 17, 2013 Issued
Array ( [id] => 9945899 [patent_doc_number] => 08995215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Semiconductor device and control method of the same' [patent_app_type] => utility [patent_app_number] => 14/081987 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11626 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081987 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/081987
Semiconductor device and control method of the same Nov 14, 2013 Issued
Array ( [id] => 9361908 [patent_doc_number] => 20140071781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY' [patent_app_type] => utility [patent_app_number] => 14/080302 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4500 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080302 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/080302
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY Nov 13, 2013 Abandoned
Array ( [id] => 9862371 [patent_doc_number] => 20150042388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/076545 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076545 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076545
Semiconductor memory apparatus Nov 10, 2013 Issued
Array ( [id] => 9337163 [patent_doc_number] => 20140063945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND DATA STORAGE SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/076704 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6682 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076704 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076704
Read method for nonvolatile memory device, and data storage system using the same Nov 10, 2013 Issued
Array ( [id] => 9305251 [patent_doc_number] => 20140043925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'DDR PSRAM AND DATA WRITING AND READING METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/054249 [patent_app_country] => US [patent_app_date] => 2013-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7170 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/054249
DDR PSRAM and data writing and reading methods thereof Oct 14, 2013 Issued
Array ( [id] => 9279379 [patent_doc_number] => 20140029347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES' [patent_app_type] => utility [patent_app_number] => 14/045857 [patent_app_country] => US [patent_app_date] => 2013-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9778 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045857 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045857
Memory system having a plurality of serially connected devices Oct 3, 2013 Issued
Array ( [id] => 9291381 [patent_doc_number] => 20140035015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'APPARATUS RELATING TO A MEMORY CELL HAVING A FLOATING BODY' [patent_app_type] => utility [patent_app_number] => 14/043476 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9182 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043476 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/043476
Apparatus relating to a memory cell having a floating body Sep 30, 2013 Issued
Array ( [id] => 9210857 [patent_doc_number] => 20140010034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'SEMICONDUCTOR DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING SAME, AND CONTROLLER FOR CONTROLLING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/019665 [patent_app_country] => US [patent_app_date] => 2013-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13328 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14019665 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/019665
Semiconductor device, information processing system including same, and controller for controlling semiconductor device Sep 5, 2013 Issued
Array ( [id] => 9261211 [patent_doc_number] => 20130343140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'Bitline for Memory' [patent_app_type] => utility [patent_app_number] => 13/964749 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5970 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964749
Bitline for memory Aug 11, 2013 Issued
Array ( [id] => 9415241 [patent_doc_number] => 08699287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Techniques for increasing a lifetime of blocks of memory' [patent_app_type] => utility [patent_app_number] => 13/962779 [patent_app_country] => US [patent_app_date] => 2013-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4471 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13962779 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/962779
Techniques for increasing a lifetime of blocks of memory Aug 7, 2013 Issued
Array ( [id] => 10889428 [patent_doc_number] => 08913430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 13/955103 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5524 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13955103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/955103
Non-volatile memory device Jul 30, 2013 Issued
Array ( [id] => 10846095 [patent_doc_number] => 08873285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Simultaneous multi-level binary search in non-volatile storage' [patent_app_type] => utility [patent_app_number] => 13/937983 [patent_app_country] => US [patent_app_date] => 2013-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 49 [patent_no_of_words] => 30443 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13937983 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/937983
Simultaneous multi-level binary search in non-volatile storage Jul 8, 2013 Issued
Array ( [id] => 9470743 [patent_doc_number] => 08724386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'nvSRAM with inverted recall' [patent_app_type] => utility [patent_app_number] => 13/921056 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921056 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/921056
nvSRAM with inverted recall Jun 17, 2013 Issued
Array ( [id] => 10583517 [patent_doc_number] => 09305641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Resistance change memory and forming method of the resistance change device' [patent_app_type] => utility [patent_app_number] => 13/905951 [patent_app_country] => US [patent_app_date] => 2013-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4724 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13905951 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/905951
Resistance change memory and forming method of the resistance change device May 29, 2013 Issued
Array ( [id] => 9119814 [patent_doc_number] => 20130286736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/903250 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903250 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/903250
Determining and using soft data in memory devices and systems May 27, 2013 Issued
Array ( [id] => 10556843 [patent_doc_number] => 09281044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Apparatuses having a ferroelectric field-effect transistor memory array and related method' [patent_app_type] => utility [patent_app_number] => 13/897037 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10515 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897037 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/897037
Apparatuses having a ferroelectric field-effect transistor memory array and related method May 16, 2013 Issued
Array ( [id] => 9133423 [patent_doc_number] => 20130294137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED' [patent_app_type] => utility [patent_app_number] => 13/888637 [patent_app_country] => US [patent_app_date] => 2013-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6576 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888637 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/888637
SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED May 6, 2013 Abandoned
Array ( [id] => 10910820 [patent_doc_number] => 20140313836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'High Speed Signaling Techniques to Improve Performance of Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 13/867259 [patent_app_country] => US [patent_app_date] => 2013-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3313 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13867259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/867259
High speed signaling techniques to improve performance of integrated circuits Apr 21, 2013 Issued
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