Search

Arezoo Sherkat

Examiner (ID: 12013)

Most Active Art Unit
2434
Art Unit(s)
2494, IPBS, 2431, 2131, 2434
Total Applications
370
Issued Applications
274
Pending Applications
15
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19085944 [patent_doc_number] => 20240112745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => NAND DATA PLACEMENT SCHEMA [patent_app_type] => utility [patent_app_number] => 18/527978 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527978 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527978
NAND data placement schema Dec 3, 2023 Issued
Array ( [id] => 19269031 [patent_doc_number] => 20240212735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => WORD LINE VOLTAGE CONTROL FOR REDUCED VOLTAGE DISTURBANCE DURING MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/524708 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524708
Word line voltage control for reduced voltage disturbance during memory operations Nov 29, 2023 Issued
Array ( [id] => 19054459 [patent_doc_number] => 20240096428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY INCLUDING A PLURALITY OF PORTIONS AND USED FOR REDUCING PROGRAM DISTURBANCE AND PROGRAM METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/518849 [patent_app_country] => US [patent_app_date] => 2023-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518849
MEMORY INCLUDING A PLURALITY OF PORTIONS AND USED FOR REDUCING PROGRAM DISTURBANCE AND PROGRAM METHOD THEREOF Nov 23, 2023 Pending
Array ( [id] => 19269030 [patent_doc_number] => 20240212734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => PLATE LINE DRIVERS WITH A SHARED BIAS DEVICE [patent_app_type] => utility [patent_app_number] => 18/518090 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518090 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518090
PLATE LINE DRIVERS WITH A SHARED BIAS DEVICE Nov 21, 2023 Pending
Array ( [id] => 19348925 [patent_doc_number] => 20240257889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => STORAGE DEVICES HAVING ENHANCED ERROR DETECTION AND MEMORY CELL REPAIR [patent_app_type] => utility [patent_app_number] => 18/508903 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508903 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508903
Storage devices having enhanced error detection and memory cell repair Nov 13, 2023 Issued
Array ( [id] => 18993036 [patent_doc_number] => 20240065005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => 3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH BIT-LINE PILLARS [patent_app_type] => utility [patent_app_number] => 18/384304 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384304 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384304
3D memory semiconductor devices and structures with bit-line pillars Oct 25, 2023 Issued
Array ( [id] => 20455753 [patent_doc_number] => 12518813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Sense counter-pulse for reading state-programmable memory cells [patent_app_type] => utility [patent_app_number] => 18/489036 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 2514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489036 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489036
Sense counter-pulse for reading state-programmable memory cells Oct 17, 2023 Issued
Array ( [id] => 18957655 [patent_doc_number] => 20240045982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SYSTEMS AND METHODS FOR USE IN SECURING BACKUP DATA FILES [patent_app_type] => utility [patent_app_number] => 18/381588 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18381588 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/381588
Systems and methods for use in securing backup data files Oct 17, 2023 Issued
Array ( [id] => 20305211 [patent_doc_number] => 12451207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor devices for detecting defects in error correction circuits, and methods of performing test mode operations [patent_app_type] => utility [patent_app_number] => 18/489567 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4170 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489567
Semiconductor devices for detecting defects in error correction circuits, and methods of performing test mode operations Oct 17, 2023 Issued
Array ( [id] => 19828595 [patent_doc_number] => 12249386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Memory, memory system and operation method of memory system [patent_app_type] => utility [patent_app_number] => 18/482016 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5072 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482016 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482016
Memory, memory system and operation method of memory system Oct 5, 2023 Issued
Array ( [id] => 19494098 [patent_doc_number] => 12112819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Apparatus for determining memory cell data states [patent_app_type] => utility [patent_app_number] => 18/376198 [patent_app_country] => US [patent_app_date] => 2023-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376198
Apparatus for determining memory cell data states Oct 2, 2023 Issued
Array ( [id] => 19878813 [patent_doc_number] => 20250111070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => AUTHORIZATION ON USER DEFINED ENTITY TYPES [patent_app_type] => utility [patent_app_number] => 18/375252 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/375252
AUTHORIZATION ON USER DEFINED ENTITY TYPES Sep 28, 2023 Pending
Array ( [id] => 19506694 [patent_doc_number] => 12118115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Virtualizing secure storage of a baseboard management controller to a host computing device [patent_app_type] => utility [patent_app_number] => 18/468075 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468075 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/468075
Virtualizing secure storage of a baseboard management controller to a host computing device Sep 14, 2023 Issued
Array ( [id] => 20389124 [patent_doc_number] => 12488857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Static random access memory (SRAM) fault correction [patent_app_type] => utility [patent_app_number] => 18/466110 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12185 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/466110
Static random access memory (SRAM) fault correction Sep 12, 2023 Issued
Array ( [id] => 19053418 [patent_doc_number] => 20240095387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/462525 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462525
Image processing apparatus, image processing method, and non-transitory computer-readable storage medium Sep 6, 2023 Issued
Array ( [id] => 20111298 [patent_doc_number] => 12362033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor module for performing error correction operation [patent_app_type] => utility [patent_app_number] => 18/459930 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459930 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459930
Semiconductor module for performing error correction operation Aug 31, 2023 Issued
Array ( [id] => 19679124 [patent_doc_number] => 12190995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory device and memory system including the same [patent_app_type] => utility [patent_app_number] => 18/455904 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455904
Memory device and memory system including the same Aug 24, 2023 Issued
Array ( [id] => 20146585 [patent_doc_number] => 12380931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Cross-temperature compensation in a memory sub-system [patent_app_type] => utility [patent_app_number] => 18/237816 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237816 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237816
Cross-temperature compensation in a memory sub-system Aug 23, 2023 Issued
Array ( [id] => 20404258 [patent_doc_number] => 12494238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Stochastic computing using logic-memory cells [patent_app_type] => utility [patent_app_number] => 18/454441 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 38 [patent_no_of_words] => 5378 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/454441
Stochastic computing using logic-memory cells Aug 22, 2023 Issued
Array ( [id] => 18990828 [patent_doc_number] => 20240062797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SYSTEMS AND METHODS FOR READING MULTI-BIT MRAM CELLS [patent_app_type] => utility [patent_app_number] => 18/453922 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453922
Systems and methods for reading multi-bit MRAM cells Aug 21, 2023 Issued
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