
Arezoo Sherkat
Examiner (ID: 12013)
| Most Active Art Unit | 2434 |
| Art Unit(s) | 2494, IPBS, 2431, 2131, 2434 |
| Total Applications | 370 |
| Issued Applications | 274 |
| Pending Applications | 15 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8579279
[patent_doc_number] => 08345499
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-01
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/396092
[patent_app_country] => US
[patent_app_date] => 2012-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3884
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13396092
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/396092 | Semiconductor device | Feb 13, 2012 | Issued |
Array
(
[id] => 8354974
[patent_doc_number] => 08250320
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-08-21
[patent_title] => 'Command cancellation channel for read—modify—write operation in a memory'
[patent_app_type] => utility
[patent_app_number] => 13/366757
[patent_app_country] => US
[patent_app_date] => 2012-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 9200
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366757
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/366757 | Command cancellation channel for read—modify—write operation in a memory | Feb 5, 2012 | Issued |
Array
(
[id] => 10868120
[patent_doc_number] => RE045259
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2014-11-25
[patent_title] => 'Hit ahead hierarchical scalable priority encoding logic and circuits'
[patent_app_type] => reissue
[patent_app_number] => 13/355449
[patent_app_country] => US
[patent_app_date] => 2012-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3856
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13355449
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/355449 | Hit ahead hierarchical scalable priority encoding logic and circuits | Jan 19, 2012 | Issued |
Array
(
[id] => 8182581
[patent_doc_number] => 20120113738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-10
[patent_title] => 'Memory Device Having Multiple Power Modes'
[patent_app_type] => utility
[patent_app_number] => 13/352177
[patent_app_country] => US
[patent_app_date] => 2012-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4036
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20120113738.pdf
[firstpage_image] =>[orig_patent_app_number] => 13352177
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/352177 | Memory device having multiple power modes | Jan 16, 2012 | Issued |
Array
(
[id] => 8644187
[patent_doc_number] => 08369181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-05
[patent_title] => 'Semiconductor integrated circuit device for controlling a sense amplifier'
[patent_app_type] => utility
[patent_app_number] => 13/340812
[patent_app_country] => US
[patent_app_date] => 2011-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4080
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340812
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/340812 | Semiconductor integrated circuit device for controlling a sense amplifier | Dec 29, 2011 | Issued |
Array
(
[id] => 8369438
[patent_doc_number] => 20120218831
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'INTEGRATED CIRCUIT FOR STORING INFORMATION'
[patent_app_type] => utility
[patent_app_number] => 13/331921
[patent_app_country] => US
[patent_app_date] => 2011-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3132
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331921
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/331921 | Integrated circuit for storing information | Dec 19, 2011 | Issued |
Array
(
[id] => 9531342
[patent_doc_number] => 08755223
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-17
[patent_title] => 'Three dimensional non-volatile storage with asymmetrical vertical select devices'
[patent_app_type] => utility
[patent_app_number] => 13/323717
[patent_app_country] => US
[patent_app_date] => 2011-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 56
[patent_figures_cnt] => 64
[patent_no_of_words] => 32701
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323717
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/323717 | Three dimensional non-volatile storage with asymmetrical vertical select devices | Dec 11, 2011 | Issued |
Array
(
[id] => 8052417
[patent_doc_number] => 20120075942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-29
[patent_title] => 'ROW ADDRESS DECODER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/309818
[patent_app_country] => US
[patent_app_date] => 2011-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4427
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20120075942.pdf
[firstpage_image] =>[orig_patent_app_number] => 13309818
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/309818 | Row address decoder and semiconductor memory device having the same | Dec 1, 2011 | Issued |
Array
(
[id] => 10512662
[patent_doc_number] => 09240240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-19
[patent_title] => 'Apparatus having indications of memory cell density and methods of their determination and use'
[patent_app_type] => utility
[patent_app_number] => 13/306227
[patent_app_country] => US
[patent_app_date] => 2011-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7775
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13306227
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/306227 | Apparatus having indications of memory cell density and methods of their determination and use | Nov 28, 2011 | Issued |
Array
(
[id] => 10125052
[patent_doc_number] => 09159418
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-10-13
[patent_title] => 'High density stacked CNT memory cube arrays with memory selectors'
[patent_app_type] => utility
[patent_app_number] => 13/301521
[patent_app_country] => US
[patent_app_date] => 2011-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 5181
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301521
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/301521 | High density stacked CNT memory cube arrays with memory selectors | Nov 20, 2011 | Issued |
Array
(
[id] => 8195331
[patent_doc_number] => 20120120715
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/293173
[patent_app_country] => US
[patent_app_date] => 2011-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 33304
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20120120715.pdf
[firstpage_image] =>[orig_patent_app_number] => 13293173
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/293173 | Semiconductor device | Nov 9, 2011 | Issued |
Array
(
[id] => 8676996
[patent_doc_number] => 08385118
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-26
[patent_title] => 'Multi-pass programming in a memory device'
[patent_app_type] => utility
[patent_app_number] => 13/286390
[patent_app_country] => US
[patent_app_date] => 2011-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3576
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13286390
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/286390 | Multi-pass programming in a memory device | Oct 31, 2011 | Issued |
Array
(
[id] => 8508177
[patent_doc_number] => 20120307584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-06
[patent_title] => 'MEMORY POWER SUPPLY CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/283611
[patent_app_country] => US
[patent_app_date] => 2011-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1804
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283611
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/283611 | Memory power supply circuit | Oct 27, 2011 | Issued |
Array
(
[id] => 10846089
[patent_doc_number] => 08873280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Spin transfer torque random access memory'
[patent_app_type] => utility
[patent_app_number] => 13/282771
[patent_app_country] => US
[patent_app_date] => 2011-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2370
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 413
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13282771
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/282771 | Spin transfer torque random access memory | Oct 26, 2011 | Issued |
Array
(
[id] => 8238948
[patent_doc_number] => 20120147685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-14
[patent_title] => 'SEMICONDUCTOR STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/279425
[patent_app_country] => US
[patent_app_date] => 2011-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 6695
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13279425
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/279425 | Semiconductor storage device | Oct 23, 2011 | Issued |
Array
(
[id] => 8195367
[patent_doc_number] => 20120120753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'Semiconductor device having point-shift type FIFO circuit'
[patent_app_type] => utility
[patent_app_number] => 13/317601
[patent_app_country] => US
[patent_app_date] => 2011-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11107
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20120120753.pdf
[firstpage_image] =>[orig_patent_app_number] => 13317601
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/317601 | Semiconductor device having point-shift type FIFO circuit | Oct 23, 2011 | Issued |
Array
(
[id] => 9313340
[patent_doc_number] => 08654567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-18
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 13/277377
[patent_app_country] => US
[patent_app_date] => 2011-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 50
[patent_no_of_words] => 18224
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13277377
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/277377 | Semiconductor memory device | Oct 19, 2011 | Issued |
Array
(
[id] => 9498304
[patent_doc_number] => 08737133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-27
[patent_title] => 'Shifting cell voltage based on grouping of solid-state, non-volatile memory cells'
[patent_app_type] => utility
[patent_app_number] => 13/275675
[patent_app_country] => US
[patent_app_date] => 2011-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 7755
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13275675
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/275675 | Shifting cell voltage based on grouping of solid-state, non-volatile memory cells | Oct 17, 2011 | Issued |
Array
(
[id] => 10846091
[patent_doc_number] => 08873282
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Interfaces and die packages, and appartuses including the same'
[patent_app_type] => utility
[patent_app_number] => 13/276047
[patent_app_country] => US
[patent_app_date] => 2011-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8644
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276047
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/276047 | Interfaces and die packages, and appartuses including the same | Oct 17, 2011 | Issued |
Array
(
[id] => 9609893
[patent_doc_number] => 08787074
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-22
[patent_title] => 'Static random access memory test structure'
[patent_app_type] => utility
[patent_app_number] => 13/273271
[patent_app_country] => US
[patent_app_date] => 2011-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4724
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13273271
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/273271 | Static random access memory test structure | Oct 13, 2011 | Issued |