
Arezoo Sherkat
Examiner (ID: 12013)
| Most Active Art Unit | 2434 |
| Art Unit(s) | 2494, IPBS, 2431, 2131, 2434 |
| Total Applications | 370 |
| Issued Applications | 274 |
| Pending Applications | 15 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8052349
[patent_doc_number] => 20120075906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-29
[patent_title] => 'Resistance Based Memory Having Two-Diode Access Device'
[patent_app_type] => utility
[patent_app_number] => 12/892237
[patent_app_country] => US
[patent_app_date] => 2010-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8695
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20120075906.pdf
[firstpage_image] =>[orig_patent_app_number] => 12892237
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/892237 | Resistance based memory having two-diode access device | Sep 27, 2010 | Issued |
Array
(
[id] => 10106478
[patent_doc_number] => 09142262
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-22
[patent_title] => 'Stacked semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/502093
[patent_app_country] => US
[patent_app_date] => 2010-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5049
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13502093
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/502093 | Stacked semiconductor device | Sep 23, 2010 | Issued |
Array
(
[id] => 8052399
[patent_doc_number] => 20120075934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-29
[patent_title] => 'ACCESS LINE MANAGEMENT IN A MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/888765
[patent_app_country] => US
[patent_app_date] => 2010-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5501
[patent_no_of_claims] => 31
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[pdf_file] => publications/A1/0075/20120075934.pdf
[firstpage_image] =>[orig_patent_app_number] => 12888765
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/888765 | Access line management in a memory device | Sep 22, 2010 | Issued |
Array
(
[id] => 8871861
[patent_doc_number] => 08467243
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-06-18
[patent_title] => 'nvSRAM with inverted recall'
[patent_app_type] => utility
[patent_app_number] => 12/888737
[patent_app_country] => US
[patent_app_date] => 2010-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5042
[patent_no_of_claims] => 20
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12888737
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/888737 | nvSRAM with inverted recall | Sep 22, 2010 | Issued |
Array
(
[id] => 7485110
[patent_doc_number] => 20110235413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/886847
[patent_app_country] => US
[patent_app_date] => 2010-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20110235413.pdf
[firstpage_image] =>[orig_patent_app_number] => 12886847
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/886847 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE | Sep 20, 2010 | Abandoned |
Array
(
[id] => 6201114
[patent_doc_number] => 20110063900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-17
[patent_title] => 'MAGNETIC MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/885175
[patent_app_country] => US
[patent_app_date] => 2010-09-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0063/20110063900.pdf
[firstpage_image] =>[orig_patent_app_number] => 12885175
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/885175 | Magnetic memory | Sep 16, 2010 | Issued |
Array
(
[id] => 7759906
[patent_doc_number] => 20120030506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'READ DISTURB SCORECARD'
[patent_app_type] => utility
[patent_app_number] => 12/847769
[patent_app_country] => US
[patent_app_date] => 2010-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0030/20120030506.pdf
[firstpage_image] =>[orig_patent_app_number] => 12847769
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/847769 | Read disturb scorecard | Jul 29, 2010 | Issued |
Array
(
[id] => 6571300
[patent_doc_number] => 20100290285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-18
[patent_title] => 'Flash Memory Device Using Double Patterning Technology and Method of Manufacturing the Same'
[patent_app_type] => utility
[patent_app_number] => 12/845829
[patent_app_country] => US
[patent_app_date] => 2010-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 7815
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20100290285.pdf
[firstpage_image] =>[orig_patent_app_number] => 12845829
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/845829 | Flash Memory Device Using Double Patterning Technology and Method of Manufacturing the Same | Jul 28, 2010 | Abandoned |
Array
(
[id] => 7740939
[patent_doc_number] => 20120020164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-26
[patent_title] => 'TEST METHOD FOR SCREENING MANUFACTURING DEFECTS IN A MEMORY ARRAY'
[patent_app_type] => utility
[patent_app_number] => 12/842605
[patent_app_country] => US
[patent_app_date] => 2010-07-23
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4028
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[pdf_file] => publications/A1/0020/20120020164.pdf
[firstpage_image] =>[orig_patent_app_number] => 12842605
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/842605 | Test method for screening manufacturing defects in a memory array | Jul 22, 2010 | Issued |
Array
(
[id] => 7572242
[patent_doc_number] => 20110267898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-03
[patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/841053
[patent_app_country] => US
[patent_app_date] => 2010-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0267/20110267898.pdf
[firstpage_image] =>[orig_patent_app_number] => 12841053
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/841053 | SEMICONDUCTOR MEMORY APPARATUS | Jul 20, 2010 | Abandoned |
Array
(
[id] => 6153195
[patent_doc_number] => 20110156034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'REPAIR CIRCUIT AND REPAIR METHOD OF SEMICONDUCTOR APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/840231
[patent_app_country] => US
[patent_app_date] => 2010-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0156/20110156034.pdf
[firstpage_image] =>[orig_patent_app_number] => 12840231
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/840231 | Repair circuit and repair method of semiconductor apparatus | Jul 19, 2010 | Issued |
Array
(
[id] => 6512267
[patent_doc_number] => 20100261317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-14
[patent_title] => 'OFFSET NON-VOLATILE STORAGE'
[patent_app_type] => utility
[patent_app_number] => 12/822568
[patent_app_country] => US
[patent_app_date] => 2010-06-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0261/20100261317.pdf
[firstpage_image] =>[orig_patent_app_number] => 12822568
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/822568 | Offset non-volatile storage | Jun 23, 2010 | Issued |
Array
(
[id] => 7528785
[patent_doc_number] => 08045388
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[patent_issue_date] => 2011-10-25
[patent_title] => 'Semiconductor device and control method of the same'
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[pdf_file] => patents/08/045/08045388.pdf
[firstpage_image] =>[orig_patent_app_number] => 12819071
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/819071 | Semiconductor device and control method of the same | Jun 17, 2010 | Issued |
Array
(
[id] => 8847738
[patent_doc_number] => 08456928
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[patent_issue_date] => 2013-06-04
[patent_title] => 'Dynamic adjustment of reference voltage in a computer memory system'
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12785697
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/785697 | Dynamic adjustment of reference voltage in a computer memory system | May 23, 2010 | Issued |
Array
(
[id] => 7485143
[patent_doc_number] => 20110235426
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[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'FLASH MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES'
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[firstpage_image] =>[orig_patent_app_number] => 12782911
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/782911 | Memory system having a plurality of serially connected devices | May 18, 2010 | Issued |
Array
(
[id] => 8835899
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[patent_title] => 'Determining and using soft data in memory devices and systems'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/778577 | Determining and using soft data in memory devices and systems | May 11, 2010 | Issued |
Array
(
[id] => 7585582
[patent_doc_number] => 20110280092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-17
[patent_title] => 'Multi-Bank Read/Write To Reduce Test-Time In Memories'
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[patent_app_number] => 12/777687
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/777687 | Multi-Bank Read/Write To Reduce Test-Time In Memories | May 10, 2010 | Abandoned |
Array
(
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Array
(
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Array
(
[id] => 8970191
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[patent_title] => 'Partitioned bitline for memory'
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12772147
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/772147 | Partitioned bitline for memory | Apr 29, 2010 | Issued |