Search

Arezoo Sherkat

Examiner (ID: 12013)

Most Active Art Unit
2434
Art Unit(s)
2494, IPBS, 2431, 2131, 2434
Total Applications
370
Issued Applications
274
Pending Applications
15
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7718431 [patent_doc_number] => 08095756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-10 [patent_title] => 'System and method for coordinating deduplication operations and backup operations of a storage volume' [patent_app_type] => utility [patent_app_number] => 12/431510 [patent_app_country] => US [patent_app_date] => 2009-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9719 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095756.pdf [firstpage_image] =>[orig_patent_app_number] => 12431510 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431510
System and method for coordinating deduplication operations and backup operations of a storage volume Apr 27, 2009 Issued
Array ( [id] => 7718430 [patent_doc_number] => 08095755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'System, method and computer program product for generating a consistent point in time copy of data' [patent_app_type] => utility [patent_app_number] => 12/430149 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7426 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095755.pdf [firstpage_image] =>[orig_patent_app_number] => 12430149 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430149
System, method and computer program product for generating a consistent point in time copy of data Apr 26, 2009 Issued
Array ( [id] => 6596536 [patent_doc_number] => 20100275193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'REDUCING MEMORY USAGE OF KERNEL MEMORY MANAGEMENT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/429755 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4303 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275193.pdf [firstpage_image] =>[orig_patent_app_number] => 12429755 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/429755
Reducing memory usage of kernel memory management structures Apr 23, 2009 Issued
Array ( [id] => 135469 [patent_doc_number] => 07697360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/426715 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 9298 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/697/07697360.pdf [firstpage_image] =>[orig_patent_app_number] => 12426715 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426715
Semiconductor device Apr 19, 2009 Issued
Array ( [id] => 7746297 [patent_doc_number] => 08108640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-31 [patent_title] => 'Reserving a thin provisioned space in a storage system' [patent_app_type] => utility [patent_app_number] => 12/425300 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8643 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108640.pdf [firstpage_image] =>[orig_patent_app_number] => 12425300 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/425300
Reserving a thin provisioned space in a storage system Apr 15, 2009 Issued
Array ( [id] => 5463190 [patent_doc_number] => 20090323390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/422083 [patent_app_country] => US [patent_app_date] => 2009-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8955 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20090323390.pdf [firstpage_image] =>[orig_patent_app_number] => 12422083 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/422083
SEMICONDUCTOR MEMORY DEVICE Apr 9, 2009 Abandoned
Array ( [id] => 8030875 [patent_doc_number] => 08144529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'System and method for delay locked loop relock mode' [patent_app_type] => utility [patent_app_number] => 12/415971 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/144/08144529.pdf [firstpage_image] =>[orig_patent_app_number] => 12415971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/415971
System and method for delay locked loop relock mode Mar 30, 2009 Issued
Array ( [id] => 5301846 [patent_doc_number] => 20090296498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Memory access method and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/382243 [patent_app_country] => US [patent_app_date] => 2009-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6648 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20090296498.pdf [firstpage_image] =>[orig_patent_app_number] => 12382243 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/382243
Memory access method and semiconductor memory device Mar 10, 2009 Issued
Array ( [id] => 10047204 [patent_doc_number] => 09087603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Method and apparatus for selective DRAM precharge' [patent_app_type] => utility [patent_app_number] => 12/369105 [patent_app_country] => US [patent_app_date] => 2009-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6801 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12369105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/369105
Method and apparatus for selective DRAM precharge Feb 10, 2009 Issued
Array ( [id] => 5544398 [patent_doc_number] => 20090154275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/369201 [patent_app_country] => US [patent_app_date] => 2009-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6256 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20090154275.pdf [firstpage_image] =>[orig_patent_app_number] => 12369201 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/369201
SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF Feb 10, 2009 Abandoned
Array ( [id] => 10047204 [patent_doc_number] => 09087603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Method and apparatus for selective DRAM precharge' [patent_app_type] => utility [patent_app_number] => 12/369105 [patent_app_country] => US [patent_app_date] => 2009-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6801 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12369105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/369105
Method and apparatus for selective DRAM precharge Feb 10, 2009 Issued
Array ( [id] => 6470458 [patent_doc_number] => 20100091582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 12/365589 [patent_app_country] => US [patent_app_date] => 2009-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6584 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091582.pdf [firstpage_image] =>[orig_patent_app_number] => 12365589 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/365589
Architecture and method for memory programming Feb 3, 2009 Issued
Array ( [id] => 6479481 [patent_doc_number] => 20100192000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus' [patent_app_type] => utility [patent_app_number] => 12/361836 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20100192000.pdf [firstpage_image] =>[orig_patent_app_number] => 12361836 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361836
Setting controller termination in a memory controller and memory device interface in a communication bus Jan 28, 2009 Issued
Array ( [id] => 8154820 [patent_doc_number] => 08169841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Strobe apparatus, systems, and methods' [patent_app_type] => utility [patent_app_number] => 12/358977 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4705 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169841.pdf [firstpage_image] =>[orig_patent_app_number] => 12358977 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/358977
Strobe apparatus, systems, and methods Jan 22, 2009 Issued
Array ( [id] => 8539355 [patent_doc_number] => 08315078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Power saving static-based comparator circuits and methods and content-addressable memory (CAM) circuits employing same' [patent_app_type] => utility [patent_app_number] => 12/357767 [patent_app_country] => US [patent_app_date] => 2009-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8085 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12357767 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/357767
Power saving static-based comparator circuits and methods and content-addressable memory (CAM) circuits employing same Jan 21, 2009 Issued
Array ( [id] => 6227646 [patent_doc_number] => 20100182827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'High Margin Multilevel Phase-Change Memory via Pulse Width Programming' [patent_app_type] => utility [patent_app_number] => 12/357781 [patent_app_country] => US [patent_app_date] => 2009-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182827.pdf [firstpage_image] =>[orig_patent_app_number] => 12357781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/357781
High Margin Multilevel Phase-Change Memory via Pulse Width Programming Jan 21, 2009 Abandoned
Array ( [id] => 6227701 [patent_doc_number] => 20100182850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'DYNAMIC LEAKAGE CONTROL FOR MEMORY ARRAYS' [patent_app_type] => utility [patent_app_number] => 12/355389 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4515 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182850.pdf [firstpage_image] =>[orig_patent_app_number] => 12355389 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/355389
Dynamic leakage control for memory arrays Jan 15, 2009 Issued
Array ( [id] => 8030895 [patent_doc_number] => 08144538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/320037 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3842 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/144/08144538.pdf [firstpage_image] =>[orig_patent_app_number] => 12320037 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/320037
Semiconductor device Jan 14, 2009 Issued
Array ( [id] => 6390823 [patent_doc_number] => 20100177560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/354121 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7338 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20100177560.pdf [firstpage_image] =>[orig_patent_app_number] => 12354121 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354121
Non-volatile memory circuit including voltage divider with phase change memory devices Jan 14, 2009 Issued
Array ( [id] => 5478793 [patent_doc_number] => 20090201750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF MEASURING A MAXIMUM DELAY' [patent_app_type] => utility [patent_app_number] => 12/354209 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7430 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20090201750.pdf [firstpage_image] =>[orig_patent_app_number] => 12354209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354209
Semiconductor integrated circuit and method of measuring a maximum delay Jan 14, 2009 Issued
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