Search

Arezoo Sherkat

Examiner (ID: 12013)

Most Active Art Unit
2434
Art Unit(s)
2494, IPBS, 2431, 2131, 2434
Total Applications
370
Issued Applications
274
Pending Applications
15
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8216630 [patent_doc_number] => 08194437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Computer memory device with multiple interfaces' [patent_app_type] => utility [patent_app_number] => 12/352713 [patent_app_country] => US [patent_app_date] => 2009-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4041 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/194/08194437.pdf [firstpage_image] =>[orig_patent_app_number] => 12352713 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352713
Computer memory device with multiple interfaces Jan 12, 2009 Issued
Array ( [id] => 4515163 [patent_doc_number] => 07916531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Memory elements and methods of using the same' [patent_app_type] => utility [patent_app_number] => 12/351872 [patent_app_country] => US [patent_app_date] => 2009-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/916/07916531.pdf [firstpage_image] =>[orig_patent_app_number] => 12351872 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/351872
Memory elements and methods of using the same Jan 11, 2009 Issued
Array ( [id] => 5314771 [patent_doc_number] => 20090279369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'DATA OUTPUT APPARATUS AND METHOD FOR OUTPUTTING DATA THEREOF' [patent_app_type] => utility [patent_app_number] => 12/347287 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2988 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20090279369.pdf [firstpage_image] =>[orig_patent_app_number] => 12347287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/347287
Data output apparatus and method for outputting data thereof Dec 30, 2008 Issued
Array ( [id] => 8117343 [patent_doc_number] => 08159898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Architecture of highly integrated semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/346311 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4448 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159898.pdf [firstpage_image] =>[orig_patent_app_number] => 12346311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346311
Architecture of highly integrated semiconductor memory device Dec 29, 2008 Issued
Array ( [id] => 6616442 [patent_doc_number] => 20100034036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR CONTROLLING A SENSE AMPLIFIER' [patent_app_type] => utility [patent_app_number] => 12/345665 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20100034036.pdf [firstpage_image] =>[orig_patent_app_number] => 12345665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345665
Semiconductor integrated circuit device for controlling a sense amplifier Dec 29, 2008 Issued
Array ( [id] => 7551941 [patent_doc_number] => 08064278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Protection register for a non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/346701 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5056 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/064/08064278.pdf [firstpage_image] =>[orig_patent_app_number] => 12346701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346701
Protection register for a non-volatile memory Dec 29, 2008 Issued
Array ( [id] => 5579717 [patent_doc_number] => 20090175063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL ARRAY HAVING MEMORY CELLS USING FLOATING BODY TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/344765 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7373 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20090175063.pdf [firstpage_image] =>[orig_patent_app_number] => 12344765 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344765
Semiconductor memory device including memory cell array having memory cells using floating body transistors Dec 28, 2008 Issued
Array ( [id] => 7802276 [patent_doc_number] => 08130552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Multi-pass programming for memory with reduced data storage requirement' [patent_app_type] => utility [patent_app_number] => 12/344763 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 14449 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/130/08130552.pdf [firstpage_image] =>[orig_patent_app_number] => 12344763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344763
Multi-pass programming for memory with reduced data storage requirement Dec 28, 2008 Issued
Array ( [id] => 6403490 [patent_doc_number] => 20100165707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors' [patent_app_type] => utility [patent_app_number] => 12/345125 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3418 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165707.pdf [firstpage_image] =>[orig_patent_app_number] => 12345125 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345125
Read/write margin improvement in SRAM design using dual-gate transistors Dec 28, 2008 Issued
Array ( [id] => 7980163 [patent_doc_number] => 08072835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Row address decoder and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 12/344841 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4429 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072835.pdf [firstpage_image] =>[orig_patent_app_number] => 12344841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344841
Row address decoder and semiconductor memory device having the same Dec 28, 2008 Issued
Array ( [id] => 5433908 [patent_doc_number] => 20090168494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Semiconductor device having resistance based memory array, method of operation, and systems associated therewith' [patent_app_type] => utility [patent_app_number] => 12/318241 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8524 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168494.pdf [firstpage_image] =>[orig_patent_app_number] => 12318241 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/318241
Semiconductor device having resistance based memory array, method of operation, and systems associated therewith Dec 22, 2008 Issued
Array ( [id] => 5584182 [patent_doc_number] => 20090103384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 12/341316 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10757 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103384.pdf [firstpage_image] =>[orig_patent_app_number] => 12341316 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341316
Apparatus and method for self-refreshing dynamic random access memory cells Dec 21, 2008 Issued
Array ( [id] => 4474540 [patent_doc_number] => 07944728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Programming a memory cell with a diode in series by applying reverse bias' [patent_app_type] => utility [patent_app_number] => 12/318021 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6916 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944728.pdf [firstpage_image] =>[orig_patent_app_number] => 12318021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/318021
Programming a memory cell with a diode in series by applying reverse bias Dec 18, 2008 Issued
Array ( [id] => 5433976 [patent_doc_number] => 20090168562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR DEVICE, INFORMATION CONTROL METHOD AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/340083 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9222 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168562.pdf [firstpage_image] =>[orig_patent_app_number] => 12340083 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/340083
Semiconductor device, information control method and electronic device Dec 18, 2008 Issued
Array ( [id] => 7754082 [patent_doc_number] => 08111548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Programming non-volatile storage using binary and multi-state programming processes' [patent_app_type] => utility [patent_app_number] => 12/339005 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 12462 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/111/08111548.pdf [firstpage_image] =>[orig_patent_app_number] => 12339005 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339005
Programming non-volatile storage using binary and multi-state programming processes Dec 17, 2008 Issued
Array ( [id] => 45037 [patent_doc_number] => 07782705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Word line decoder circuit' [patent_app_type] => utility [patent_app_number] => 12/336547 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4695 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782705.pdf [firstpage_image] =>[orig_patent_app_number] => 12336547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/336547
Word line decoder circuit Dec 16, 2008 Issued
Array ( [id] => 8471293 [patent_doc_number] => 08300482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Data transfer circuit and semiconductor memory device including the same' [patent_app_type] => utility [patent_app_number] => 12/326985 [patent_app_country] => US [patent_app_date] => 2008-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6891 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12326985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/326985
Data transfer circuit and semiconductor memory device including the same Dec 2, 2008 Issued
Array ( [id] => 9217307 [patent_doc_number] => 08630113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-14 [patent_title] => 'Apparatus for memory with improved performance and associated methods' [patent_app_type] => utility [patent_app_number] => 12/277411 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 7632 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12277411 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/277411
Apparatus for memory with improved performance and associated methods Nov 24, 2008 Issued
Array ( [id] => 6554454 [patent_doc_number] => 20100127757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'EFUSE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/277495 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20100127757.pdf [firstpage_image] =>[orig_patent_app_number] => 12277495 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/277495
Efuse device Nov 24, 2008 Issued
Array ( [id] => 7551915 [patent_doc_number] => 08064252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Multi-pass programming in a memory device' [patent_app_type] => utility [patent_app_number] => 12/276085 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3506 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/064/08064252.pdf [firstpage_image] =>[orig_patent_app_number] => 12276085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/276085
Multi-pass programming in a memory device Nov 20, 2008 Issued
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