Search

Arezoo Sherkat

Examiner (ID: 12013)

Most Active Art Unit
2434
Art Unit(s)
2494, IPBS, 2431, 2131, 2434
Total Applications
370
Issued Applications
274
Pending Applications
15
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5263602 [patent_doc_number] => 20090116287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'OPERATION METHODS FOR MEMORY CELL AND ARRAY THEREOF IMMUNE TO PUNCHTHROUGH LEAKAGE' [patent_app_type] => utility [patent_app_number] => 12/264893 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 18890 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20090116287.pdf [firstpage_image] =>[orig_patent_app_number] => 12264893 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/264893
Operation methods for memory cell and array thereof immune to punchthrough leakage Nov 3, 2008 Issued
Array ( [id] => 7970023 [patent_doc_number] => 07940586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/262269 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4191 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940586.pdf [firstpage_image] =>[orig_patent_app_number] => 12262269 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/262269
Semiconductor memory device Oct 30, 2008 Issued
Array ( [id] => 4447786 [patent_doc_number] => 07864610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Sense amplifier controlling circuit and controlling method' [patent_app_type] => utility [patent_app_number] => 12/289385 [patent_app_country] => US [patent_app_date] => 2008-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9601 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/864/07864610.pdf [firstpage_image] =>[orig_patent_app_number] => 12289385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289385
Sense amplifier controlling circuit and controlling method Oct 26, 2008 Issued
Array ( [id] => 5507029 [patent_doc_number] => 20090080236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 12/211501 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11902 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080236.pdf [firstpage_image] =>[orig_patent_app_number] => 12211501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/211501
Semiconductor memory device and method for manufacturing same Sep 15, 2008 Issued
Array ( [id] => 4522094 [patent_doc_number] => 07911824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Nonvolatile memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/445383 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 20481 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/911/07911824.pdf [firstpage_image] =>[orig_patent_app_number] => 12445383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/445383
Nonvolatile memory apparatus Jul 28, 2008 Issued
Array ( [id] => 204615 [patent_doc_number] => 07633819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator' [patent_app_type] => utility [patent_app_number] => 12/180776 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5071 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633819.pdf [firstpage_image] =>[orig_patent_app_number] => 12180776 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180776
Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator Jul 27, 2008 Issued
Array ( [id] => 5347688 [patent_doc_number] => 20090003049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'PHASE CHANGE MEMORY DEVICE AND PROGRAM METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/168742 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4567 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20090003049.pdf [firstpage_image] =>[orig_patent_app_number] => 12168742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168742
Phase change memory device and program method thereof Jul 6, 2008 Issued
Array ( [id] => 5457137 [patent_doc_number] => 20090257289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'INTERNAL VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/165057 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10037 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20090257289.pdf [firstpage_image] =>[orig_patent_app_number] => 12165057 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165057
Internal voltage generator and semiconductor memory device including the same Jun 29, 2008 Issued
Array ( [id] => 5433998 [patent_doc_number] => 20090168584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/165065 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3380 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168584.pdf [firstpage_image] =>[orig_patent_app_number] => 12165065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165065
Semiconductor memory device and operation method thereof Jun 29, 2008 Issued
Array ( [id] => 5579770 [patent_doc_number] => 20090175116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/165045 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8536 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20090175116.pdf [firstpage_image] =>[orig_patent_app_number] => 12165045 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165045
Clock synchronization circuit and operation method thereof Jun 29, 2008 Issued
Array ( [id] => 4503876 [patent_doc_number] => 07948806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Device with precharge/homogenize circuit' [patent_app_type] => utility [patent_app_number] => 12/122273 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6598 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948806.pdf [firstpage_image] =>[orig_patent_app_number] => 12122273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122273
Device with precharge/homogenize circuit May 15, 2008 Issued
Array ( [id] => 6508191 [patent_doc_number] => 20100202193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/596721 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3903 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202193.pdf [firstpage_image] =>[orig_patent_app_number] => 12596721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/596721
Non-volatile memory device Apr 29, 2008 Issued
Array ( [id] => 5484235 [patent_doc_number] => 20090274000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP' [patent_app_type] => utility [patent_app_number] => 12/112831 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4666 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20090274000.pdf [firstpage_image] =>[orig_patent_app_number] => 12112831 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112831
System and method of command based and current limit controlled memory device power up Apr 29, 2008 Issued
Array ( [id] => 4531808 [patent_doc_number] => 07952944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'System for providing on-die termination of a control signal bus' [patent_app_type] => utility [patent_app_number] => 12/112391 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8034 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952944.pdf [firstpage_image] =>[orig_patent_app_number] => 12112391 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112391
System for providing on-die termination of a control signal bus Apr 29, 2008 Issued
Array ( [id] => 4531542 [patent_doc_number] => 07952911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'SRAM cell array structure' [patent_app_type] => utility [patent_app_number] => 12/111905 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1949 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952911.pdf [firstpage_image] =>[orig_patent_app_number] => 12111905 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111905
SRAM cell array structure Apr 28, 2008 Issued
Array ( [id] => 5556955 [patent_doc_number] => 20090268532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'Systems and Methods for Writing to a Memory' [patent_app_type] => utility [patent_app_number] => 12/110859 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7739 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20090268532.pdf [firstpage_image] =>[orig_patent_app_number] => 12110859 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110859
Systems and methods for writing to a memory Apr 27, 2008 Issued
Array ( [id] => 7725245 [patent_doc_number] => 08098520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Storage device including a memory cell having multiple memory layers' [patent_app_type] => utility [patent_app_number] => 12/110099 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 10492 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/098/08098520.pdf [firstpage_image] =>[orig_patent_app_number] => 12110099 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110099
Storage device including a memory cell having multiple memory layers Apr 24, 2008 Issued
Array ( [id] => 4587715 [patent_doc_number] => 07835212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Methods and arrangements for enhancing power management systems in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/099913 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6945 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/835/07835212.pdf [firstpage_image] =>[orig_patent_app_number] => 12099913 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099913
Methods and arrangements for enhancing power management systems in integrated circuits Apr 8, 2008 Issued
Array ( [id] => 4717287 [patent_doc_number] => 20080239809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'FLASH MEMORY DEVICE AND METHOD FOR PROVIDING INITIALIZATION DATA' [patent_app_type] => utility [patent_app_number] => 12/054617 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7468 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20080239809.pdf [firstpage_image] =>[orig_patent_app_number] => 12054617 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054617
Flash memory device and method for providing initialization data Mar 24, 2008 Issued
Array ( [id] => 5471804 [patent_doc_number] => 20090244970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT AND PARALLEL STORAGE CAPACITOR' [patent_app_type] => utility [patent_app_number] => 12/054973 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4065 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20090244970.pdf [firstpage_image] =>[orig_patent_app_number] => 12054973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054973
Random access memory with CMOS-compatible nonvolatile storage element and parallel storage capacitor Mar 24, 2008 Issued
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