
Arezoo Sherkat
Examiner (ID: 12013)
| Most Active Art Unit | 2434 |
| Art Unit(s) | 2494, IPBS, 2431, 2131, 2434 |
| Total Applications | 370 |
| Issued Applications | 274 |
| Pending Applications | 15 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4531819
[patent_doc_number] => 07952946
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'No-disturb bit line write for improving speed of eDRAM'
[patent_app_type] => utility
[patent_app_number] => 12/055095
[patent_app_country] => US
[patent_app_date] => 2008-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3758
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/952/07952946.pdf
[firstpage_image] =>[orig_patent_app_number] => 12055095
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/055095 | No-disturb bit line write for improving speed of eDRAM | Mar 24, 2008 | Issued |
Array
(
[id] => 4858077
[patent_doc_number] => 20080266927
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/055035
[patent_app_country] => US
[patent_app_date] => 2008-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 7284
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20080266927.pdf
[firstpage_image] =>[orig_patent_app_number] => 12055035
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/055035 | Semiconductor integrated circuit device and method of fabricating the semiconductor integrated circuit device | Mar 24, 2008 | Issued |
Array
(
[id] => 5402658
[patent_doc_number] => 20090237972
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-24
[patent_title] => 'MEMORY INCLUDING PERIPHERY CIRCUITRY TO SUPPORT A PORTION OR ALL OF THE MULTIPLE BANKS OF MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 12/053913
[patent_app_country] => US
[patent_app_date] => 2008-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3492
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0237/20090237972.pdf
[firstpage_image] =>[orig_patent_app_number] => 12053913
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/053913 | Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells | Mar 23, 2008 | Issued |
Array
(
[id] => 4784107
[patent_doc_number] => 20080137436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/024867
[patent_app_country] => US
[patent_app_date] => 2008-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6753
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20080137436.pdf
[firstpage_image] =>[orig_patent_app_number] => 12024867
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/024867 | Programming method for non-volatile memory and non-volatile memory-based programmable logic device | Jan 31, 2008 | Issued |
Array
(
[id] => 4500808
[patent_doc_number] => 07957192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-07
[patent_title] => 'Read and volatile NV standby disturb'
[patent_app_type] => utility
[patent_app_number] => 12/006225
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2659
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/957/07957192.pdf
[firstpage_image] =>[orig_patent_app_number] => 12006225
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/006225 | Read and volatile NV standby disturb | Dec 30, 2007 | Issued |
Array
(
[id] => 4914311
[patent_doc_number] => 20080094911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'Non-Volatile Memory With Improved Program-Verify Operations'
[patent_app_type] => utility
[patent_app_number] => 11/955624
[patent_app_country] => US
[patent_app_date] => 2007-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 14117
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20080094911.pdf
[firstpage_image] =>[orig_patent_app_number] => 11955624
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/955624 | Non-volatile memory with improved program-verify operations | Dec 12, 2007 | Issued |
Array
(
[id] => 134012
[patent_doc_number] => 07701751
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-20
[patent_title] => 'One-transistor type DRAM'
[patent_app_type] => utility
[patent_app_number] => 12/000393
[patent_app_country] => US
[patent_app_date] => 2007-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 3749
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/701/07701751.pdf
[firstpage_image] =>[orig_patent_app_number] => 12000393
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000393 | One-transistor type DRAM | Dec 11, 2007 | Issued |
Array
(
[id] => 4674755
[patent_doc_number] => 20080212383
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'Circuit and method for parallel test of memory device'
[patent_app_type] => utility
[patent_app_number] => 12/000123
[patent_app_country] => US
[patent_app_date] => 2007-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3810
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20080212383.pdf
[firstpage_image] =>[orig_patent_app_number] => 12000123
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000123 | Circuit and method for parallel test of memory device | Dec 9, 2007 | Issued |
Array
(
[id] => 7531529
[patent_doc_number] => 07843758
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-30
[patent_title] => 'Multi-chip package flash memory device and method for reading status data therefrom'
[patent_app_type] => utility
[patent_app_number] => 11/984595
[patent_app_country] => US
[patent_app_date] => 2007-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6367
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/843/07843758.pdf
[firstpage_image] =>[orig_patent_app_number] => 11984595
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/984595 | Multi-chip package flash memory device and method for reading status data therefrom | Nov 19, 2007 | Issued |
Array
(
[id] => 5277031
[patent_doc_number] => 20090129163
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-21
[patent_title] => 'SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INCREASING A LIFETIME OF A PLURALITY OF BLOCKS OF MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/942631
[patent_app_country] => US
[patent_app_date] => 2007-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4373
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0129/20090129163.pdf
[firstpage_image] =>[orig_patent_app_number] => 11942631
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/942631 | System, method, and computer program product for increasing a lifetime of a plurality of blocks of memory | Nov 18, 2007 | Issued |
Array
(
[id] => 4491814
[patent_doc_number] => 07903468
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-08
[patent_title] => 'Adaptive dynamic reading of flash memories'
[patent_app_type] => utility
[patent_app_number] => 11/941945
[patent_app_country] => US
[patent_app_date] => 2007-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 10407
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/903/07903468.pdf
[firstpage_image] =>[orig_patent_app_number] => 11941945
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/941945 | Adaptive dynamic reading of flash memories | Nov 17, 2007 | Issued |
Array
(
[id] => 4770388
[patent_doc_number] => 20080056046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 11/930292
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10706
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20080056046.pdf
[firstpage_image] =>[orig_patent_app_number] => 11930292
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/930292 | Apparatus and method for self-refreshing dynamic random access memory cells | Oct 30, 2007 | Issued |
Array
(
[id] => 4531530
[patent_doc_number] => 07952910
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Memory device with split power switch'
[patent_app_type] => utility
[patent_app_number] => 11/932555
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 12732
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/952/07952910.pdf
[firstpage_image] =>[orig_patent_app_number] => 11932555
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/932555 | Memory device with split power switch | Oct 30, 2007 | Issued |
Array
(
[id] => 206415
[patent_doc_number] => 07630267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-08
[patent_title] => 'Temperature detector in an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/932451
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 2243
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/630/07630267.pdf
[firstpage_image] =>[orig_patent_app_number] => 11932451
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/932451 | Temperature detector in an integrated circuit | Oct 30, 2007 | Issued |
Array
(
[id] => 5329264
[patent_doc_number] => 20090109741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR'
[patent_app_type] => utility
[patent_app_number] => 11/924955
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5592
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20090109741.pdf
[firstpage_image] =>[orig_patent_app_number] => 11924955
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/924955 | Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator | Oct 25, 2007 | Issued |
Array
(
[id] => 4914333
[patent_doc_number] => 20080094933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'Low-power dram and method for driving the same'
[patent_app_type] => utility
[patent_app_number] => 11/976241
[patent_app_country] => US
[patent_app_date] => 2007-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3457
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20080094933.pdf
[firstpage_image] =>[orig_patent_app_number] => 11976241
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976241 | Low-power DRAM and method for driving the same | Oct 22, 2007 | Issued |
Array
(
[id] => 9346475
[patent_doc_number] => 08665629
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-04
[patent_title] => 'Condensed memory cell structure using a FinFET'
[patent_app_type] => utility
[patent_app_number] => 11/864575
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 54
[patent_no_of_words] => 12138
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11864575
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864575 | Condensed memory cell structure using a FinFET | Sep 27, 2007 | Issued |
Array
(
[id] => 4537481
[patent_doc_number] => 07924596
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-12
[patent_title] => 'Area efficient programmable read only memory (PROM) array'
[patent_app_type] => utility
[patent_app_number] => 11/861293
[patent_app_country] => US
[patent_app_date] => 2007-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2160
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/924/07924596.pdf
[firstpage_image] =>[orig_patent_app_number] => 11861293
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861293 | Area efficient programmable read only memory (PROM) array | Sep 25, 2007 | Issued |
Array
(
[id] => 4931741
[patent_doc_number] => 20080002516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'Memory Device Having a Delay Locked Loop and Multiple Power Modes'
[patent_app_type] => utility
[patent_app_number] => 11/856661
[patent_app_country] => US
[patent_app_date] => 2007-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3990
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20080002516.pdf
[firstpage_image] =>[orig_patent_app_number] => 11856661
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/856661 | Memory Device Having a Delay Locked Loop and Multiple Power Modes | Sep 16, 2007 | Abandoned |
Array
(
[id] => 4744543
[patent_doc_number] => 20080089145
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'DUAL PORT SRAM WITH DEDICATED READ AND WRITE PORTS FOR HIGH SPEED READ OPERATION AND LOW LEAKAGE'
[patent_app_type] => utility
[patent_app_number] => 11/847119
[patent_app_country] => US
[patent_app_date] => 2007-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3279
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20080089145.pdf
[firstpage_image] =>[orig_patent_app_number] => 11847119
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/847119 | Dual port SRAM with dedicated read and write ports for high speed read operation and low leakage | Aug 28, 2007 | Issued |