Arezoo Sherkat

Array ( [id] => 244274 [patent_doc_number] => 07590013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Semiconductor memory devices having variable additive latency' [patent_app_type] => utility [patent_app_number] => 11/711647 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6693 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590013.pdf [firstpage_image] =>[orig_patent_app_number] => 11711647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 346157 [patent_doc_number] => 07499349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Memory with resistance memory cell and evaluation circuit' [patent_app_type] => utility [patent_app_number] => 11/672343 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6237 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499349.pdf [firstpage_image] =>[orig_patent_app_number] => 11672343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4452957 [patent_doc_number] => 07965573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Power-up signal generator for use in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/646415 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965573.pdf [firstpage_image] =>[orig_patent_app_number] => 11646415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 346139 [patent_doc_number] => 07499331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/640291 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9896 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499331.pdf [firstpage_image] =>[orig_patent_app_number] => 11640291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5118301 [patent_doc_number] => 20070140015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/639807 [patent_app_country] => US [patent_app_date] => 2006-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3545 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20070140015.pdf [firstpage_image] =>[orig_patent_app_number] => 11639807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 84237 [patent_doc_number] => 07746706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Methods and systems for memory devices' [patent_app_type] => utility [patent_app_number] => 11/639935 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 3618 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746706.pdf [firstpage_image] =>[orig_patent_app_number] => 11639935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4865308 [patent_doc_number] => 20080144367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Sensing device for floating body cell memory and method thereof' [patent_app_type] => utility [patent_app_number] => 11/639865 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144367.pdf [firstpage_image] =>[orig_patent_app_number] => 11639865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5022885 [patent_doc_number] => 20070148851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'METHOD OF PROGRAMMING EEPROM HAVING SINGLE GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/608529 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3650 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148851.pdf [firstpage_image] =>[orig_patent_app_number] => 11608529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 115581 [patent_doc_number] => 07715268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Non-volatile storage apparatus and a control method thereof' [patent_app_type] => utility [patent_app_number] => 11/590891 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2533 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/715/07715268.pdf [firstpage_image] =>[orig_patent_app_number] => 11590891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5214874 [patent_doc_number] => 20070103954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Memory circuit' [patent_app_type] => utility [patent_app_number] => 11/590803 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5791 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103954.pdf [firstpage_image] =>[orig_patent_app_number] => 11590803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 36101 [patent_doc_number] => 07787301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Flash memory device using double patterning technology and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/590207 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 7796 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787301.pdf [firstpage_image] =>[orig_patent_app_number] => 11590207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4920603 [patent_doc_number] => 20080068917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Controller for controlling a memory component in a semiconductor memory module' [patent_app_type] => utility [patent_app_number] => 11/589983 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4075 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20080068917.pdf [firstpage_image] =>[orig_patent_app_number] => 11589983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5021141 [patent_doc_number] => 20070147107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Stacked memory cell for use in high-density CMOS SRAM' [patent_app_type] => utility [patent_app_number] => 11/588223 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4271 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20070147107.pdf [firstpage_image] =>[orig_patent_app_number] => 11588223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5039383 [patent_doc_number] => 20070091665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Phase change random access memory and method of controlling read operation thereof' [patent_app_type] => utility [patent_app_number] => 11/580087 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4811 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20070091665.pdf [firstpage_image] =>[orig_patent_app_number] => 11580087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 206323 [patent_doc_number] => 07630225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Apparatus combining once-writeable and rewriteable information storage to support data processing' [patent_app_type] => utility [patent_app_number] => 11/529555 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2689 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/630/07630225.pdf [firstpage_image] =>[orig_patent_app_number] => 11529555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4942907 [patent_doc_number] => 20080080232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Active write current adjustment for magneto-resistive random access memory' [patent_app_type] => utility [patent_app_number] => 11/529569 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080232.pdf [firstpage_image] =>[orig_patent_app_number] => 11529569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5170276 [patent_doc_number] => 20070070707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/526057 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6258 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070707.pdf [firstpage_image] =>[orig_patent_app_number] => 11526057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 105308 [patent_doc_number] => 07724597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Nonvolatile semiconductor memory device having dummy bit line with multiple sections' [patent_app_type] => utility [patent_app_number] => 11/526015 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3186 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724597.pdf [firstpage_image] =>[orig_patent_app_number] => 11526015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4937610 [patent_doc_number] => 20080074927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Memory array having an interconnect and method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/525547 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 11986 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074927.pdf [firstpage_image] =>[orig_patent_app_number] => 11525547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5147315 [patent_doc_number] => 20070047369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Semiconductor device and control method of the same' [patent_app_type] => utility [patent_app_number] => 11/514391 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8424 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047369.pdf [firstpage_image] =>[orig_patent_app_number] => 11514391 [rel_patent_id] =>[rel_patent_doc_number] =>)