Search

Arezoo Sherkat

Examiner (ID: 12013)

Most Active Art Unit
2434
Art Unit(s)
2494, IPBS, 2431, 2131, 2434
Total Applications
370
Issued Applications
274
Pending Applications
15
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 233777 [patent_doc_number] => 07599210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Nonvolatile memory cell, storage device and nonvolatile logic circuit' [patent_app_type] => utility [patent_app_number] => 11/501697 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 76 [patent_no_of_words] => 10239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/599/07599210.pdf [firstpage_image] =>[orig_patent_app_number] => 11501697 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501697
Nonvolatile memory cell, storage device and nonvolatile logic circuit Aug 9, 2006 Issued
Array ( [id] => 225897 [patent_doc_number] => 07606085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Semiconductor device and control method of the same' [patent_app_type] => utility [patent_app_number] => 11/501449 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10369 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/606/07606085.pdf [firstpage_image] =>[orig_patent_app_number] => 11501449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501449
Semiconductor device and control method of the same Aug 7, 2006 Issued
Array ( [id] => 4656216 [patent_doc_number] => 20080025077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'SYSTEMS FOR CONTROLLED PULSE OPERATIONS IN NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/461399 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10886 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025077.pdf [firstpage_image] =>[orig_patent_app_number] => 11461399 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461399
Systems for controlled pulse operations in non-volatile memory Jul 30, 2006 Issued
Array ( [id] => 4656276 [patent_doc_number] => 20080025137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/461427 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025137.pdf [firstpage_image] =>[orig_patent_app_number] => 11461427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461427
System and method for simulating an aspect of a memory circuit Jul 30, 2006 Issued
Array ( [id] => 4656231 [patent_doc_number] => 20080025092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'New cell structure with buried capacitor for soft error rate improvement' [patent_app_type] => utility [patent_app_number] => 11/495369 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025092.pdf [firstpage_image] =>[orig_patent_app_number] => 11495369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495369
Cell structure with buried capacitor for soft error rate improvement Jul 27, 2006 Issued
Array ( [id] => 4656226 [patent_doc_number] => 20080025087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'METHOD FOR FABRICATING CHARGE-TRAPPING MEMORY' [patent_app_type] => utility [patent_app_number] => 11/460497 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025087.pdf [firstpage_image] =>[orig_patent_app_number] => 11460497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460497
Method for fabricating charge-trapping memory Jul 26, 2006 Issued
Array ( [id] => 5052835 [patent_doc_number] => 20070033380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Method and device for securing an integrated circuit, in particular a microprocessor card' [patent_app_type] => utility [patent_app_number] => 11/493865 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5724 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20070033380.pdf [firstpage_image] =>[orig_patent_app_number] => 11493865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493865
Method and device for securing an integrated circuit, in particular a microprocessor card Jul 24, 2006 Issued
Array ( [id] => 4931676 [patent_doc_number] => 20080002451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'SYSTEM AND METHOD FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES' [patent_app_type] => utility [patent_app_number] => 11/427849 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3553 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20080002451.pdf [firstpage_image] =>[orig_patent_app_number] => 11427849 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/427849
System and method for differential eFUSE sensing without reference fuses Jun 29, 2006 Issued
Array ( [id] => 237049 [patent_doc_number] => 07596032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Semiconductor device and control method therefor' [patent_app_type] => utility [patent_app_number] => 11/478554 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11496 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596032.pdf [firstpage_image] =>[orig_patent_app_number] => 11478554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478554
Semiconductor device and control method therefor Jun 27, 2006 Issued
Array ( [id] => 5197926 [patent_doc_number] => 20070297244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Top Dielectric Structures in Memory Devices and Methods for Expanding a Second Bit Operation Window' [patent_app_type] => utility [patent_app_number] => 11/425541 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 13415 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20070297244.pdf [firstpage_image] =>[orig_patent_app_number] => 11425541 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/425541
Top Dielectric Structures in Memory Devices and Methods for Expanding a Second Bit Operation Window Jun 20, 2006 Abandoned
Array ( [id] => 5164392 [patent_doc_number] => 20070285976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Intergrated circuit having a precharging circuit' [patent_app_type] => utility [patent_app_number] => 11/450605 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7995 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285976.pdf [firstpage_image] =>[orig_patent_app_number] => 11450605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450605
Integrated circuit having a precharging circuit Jun 8, 2006 Issued
Array ( [id] => 233803 [patent_doc_number] => 07599236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'In-circuit Vt distribution bit counter for non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 11/448225 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2711 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/599/07599236.pdf [firstpage_image] =>[orig_patent_app_number] => 11448225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448225
In-circuit Vt distribution bit counter for non-volatile memory devices Jun 6, 2006 Issued
Array ( [id] => 7592285 [patent_doc_number] => 07652920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/444537 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 71 [patent_no_of_words] => 9700 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/652/07652920.pdf [firstpage_image] =>[orig_patent_app_number] => 11444537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444537
Semiconductor integrated circuit device May 31, 2006 Issued
Array ( [id] => 264732 [patent_doc_number] => 07570503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-04 [patent_title] => 'Ternary content addressable memory (TCAM) cells with low signal line numbers' [patent_app_type] => utility [patent_app_number] => 11/438185 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6614 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570503.pdf [firstpage_image] =>[orig_patent_app_number] => 11438185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438185
Ternary content addressable memory (TCAM) cells with low signal line numbers May 21, 2006 Issued
Array ( [id] => 5027295 [patent_doc_number] => 20070268741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Non-volatile memory cell and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/438541 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20070268741.pdf [firstpage_image] =>[orig_patent_app_number] => 11438541 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438541
Non-volatile memory cell and methods thereof May 21, 2006 Issued
Array ( [id] => 233811 [patent_doc_number] => 07599244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Semiconductor memory, memory controller and control method for semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/437719 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4321 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/599/07599244.pdf [firstpage_image] =>[orig_patent_app_number] => 11437719 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/437719
Semiconductor memory, memory controller and control method for semiconductor memory May 21, 2006 Issued
Array ( [id] => 5624113 [patent_doc_number] => 20060262618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Semiconductor device and testing method thereof' [patent_app_type] => utility [patent_app_number] => 11/436723 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6256 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20060262618.pdf [firstpage_image] =>[orig_patent_app_number] => 11436723 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/436723
Semiconductor device and testing method thereof May 18, 2006 Abandoned
Array ( [id] => 5624120 [patent_doc_number] => 20060262625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/434897 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9222 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20060262625.pdf [firstpage_image] =>[orig_patent_app_number] => 11434897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/434897
Semiconductor device May 16, 2006 Issued
Array ( [id] => 5209302 [patent_doc_number] => 20070247886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Memory circuit' [patent_app_type] => utility [patent_app_number] => 11/406585 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247886.pdf [firstpage_image] =>[orig_patent_app_number] => 11406585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406585
Memory circuit Apr 18, 2006 Issued
Array ( [id] => 5210502 [patent_doc_number] => 20070249086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Phase change memory' [patent_app_type] => utility [patent_app_number] => 11/407345 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5719 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249086.pdf [firstpage_image] =>[orig_patent_app_number] => 11407345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407345
Phase change memory Apr 18, 2006 Abandoned
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