Search

Aric Lin

Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
60
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15623291 [patent_doc_number] => 20200082050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => FAILSAFE CIRCUIT, LAYOUT, DEVICE, AND METHOD [patent_app_type] => utility [patent_app_number] => 16/237165 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237165
Failsafe circuit, layout, device, and method Dec 30, 2018 Issued
Array ( [id] => 16117025 [patent_doc_number] => 20200210535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => METHOD AND SYSTEM FOR AUTOMATED DESIGN AND DESIGN-SPACE EXPLORATION [patent_app_type] => utility [patent_app_number] => 16/237429 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237429
Method and system for automated design and design-space exploration Dec 30, 2018 Issued
Array ( [id] => 16117023 [patent_doc_number] => 20200210534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => INTEGRATED CIRCUITRY DEVELOPMENT SYSTEM, INTEGRATED CIRCUITRY DEVELOPMENT METHOD, AND INTEGRATED CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/236758 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236758
INTEGRATED CIRCUITRY DEVELOPMENT SYSTEM, INTEGRATED CIRCUITRY DEVELOPMENT METHOD, AND INTEGRATED CIRCUITRY Dec 30, 2018 Abandoned
Array ( [id] => 16117043 [patent_doc_number] => 20200210544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SYSTEM AND METHOD FOR REDUCING SILICON AREA OF RESILIENT SYSTEMS USING FUNCTIONAL AND DUPLICATE LOGIC [patent_app_type] => utility [patent_app_number] => 16/236350 [patent_app_country] => US [patent_app_date] => 2018-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236350
SYSTEM AND METHOD FOR REDUCING SILICON AREA OF RESILIENT SYSTEMS USING FUNCTIONAL AND DUPLICATE LOGIC Dec 28, 2018 Abandoned
Array ( [id] => 15426301 [patent_doc_number] => 10546080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-28 [patent_title] => Method and system for identifying potential causes of failure in simulation runs using machine learning [patent_app_type] => utility [patent_app_number] => 16/233590 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/233590
Method and system for identifying potential causes of failure in simulation runs using machine learning Dec 26, 2018 Issued
Array ( [id] => 16494714 [patent_doc_number] => 10860757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Multicorner skew scheduling circuit design [patent_app_type] => utility [patent_app_number] => 16/232794 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232794 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232794
Multicorner skew scheduling circuit design Dec 25, 2018 Issued
Array ( [id] => 14539739 [patent_doc_number] => 20190205491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => METHOD AND APPARATUS OF EMULATION TECHNIQUES FOR ENHANCED FPGA VALIDATION [patent_app_type] => utility [patent_app_number] => 16/232583 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232583
METHOD AND APPARATUS OF EMULATION TECHNIQUES FOR ENHANCED FPGA VALIDATION Dec 25, 2018 Abandoned
Array ( [id] => 14509115 [patent_doc_number] => 20190198212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => PERSONAL ELECTRONIC DEVICE CASE AND MOUNTING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/227663 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227663
PERSONAL ELECTRONIC DEVICE CASE AND MOUNTING SYSTEM Dec 19, 2018 Abandoned
Array ( [id] => 14510927 [patent_doc_number] => 20190199118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => CHARGING STATION MOUNTED ON A POWERED DRIVEABLE MACHINE [patent_app_type] => utility [patent_app_number] => 16/226809 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226809
CHARGING STATION MOUNTED ON A POWERED DRIVEABLE MACHINE Dec 19, 2018 Abandoned
Array ( [id] => 16700432 [patent_doc_number] => 10951049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Battery charging circuit with improved system stability and control method thereof [patent_app_type] => utility [patent_app_number] => 16/228241 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7006 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228241
Battery charging circuit with improved system stability and control method thereof Dec 19, 2018 Issued
Array ( [id] => 16099953 [patent_doc_number] => 20200203963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => CELL BALANCER [patent_app_type] => utility [patent_app_number] => 16/227122 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227122
CELL BALANCER Dec 19, 2018 Abandoned
Array ( [id] => 17026012 [patent_doc_number] => 20210249884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Charging Device and Charging System [patent_app_type] => utility [patent_app_number] => 17/269340 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17269340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/269340
Charging Device and Charging System Dec 18, 2018 Abandoned
Array ( [id] => 17083458 [patent_doc_number] => 20210278464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => CONDITION ASSESSMENT METHOD AND DEVICE FOR AN OUTDOOR POST-MOUNTED VACUUM SWITCH [patent_app_type] => utility [patent_app_number] => 16/497644 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16497644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/497644
CONDITION ASSESSMENT METHOD AND DEVICE FOR AN OUTDOOR POST-MOUNTED VACUUM SWITCH Dec 10, 2018 Abandoned
Array ( [id] => 14443353 [patent_doc_number] => 20190179549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => STOCHASTIC DATA-DRIVEN DYNAMIC LOGIC REALLOCATION AND LOGIC CACHE METHOD FOR RUN-TIME ADAPTIVE COMPUTING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/213235 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213235
STOCHASTIC DATA-DRIVEN DYNAMIC LOGIC REALLOCATION AND LOGIC CACHE METHOD FOR RUN-TIME ADAPTIVE COMPUTING ARCHITECTURE Dec 6, 2018 Abandoned
Array ( [id] => 18204398 [patent_doc_number] => 11586793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Method for producing an association list [patent_app_type] => utility [patent_app_number] => 16/188893 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4354 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188893
Method for producing an association list Nov 12, 2018 Issued
Array ( [id] => 16033117 [patent_doc_number] => 10678982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information [patent_app_type] => utility [patent_app_number] => 16/173583 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/173583
System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information Oct 28, 2018 Issued
Array ( [id] => 13956973 [patent_doc_number] => 20190054830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => METHOD AND DEVICE FOR PROVIDING ELECTRICAL ENERGY [patent_app_type] => utility [patent_app_number] => 16/164109 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16164109 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/164109
METHOD AND DEVICE FOR PROVIDING ELECTRICAL ENERGY Oct 17, 2018 Abandoned
Array ( [id] => 17409309 [patent_doc_number] => 11250196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Conductor subdivision in physical integrated circuit layout for parasitic extraction [patent_app_type] => utility [patent_app_number] => 16/119906 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119906
Conductor subdivision in physical integrated circuit layout for parasitic extraction Aug 30, 2018 Issued
Array ( [id] => 17515896 [patent_doc_number] => 11295051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => System and method for interactively controlling the course of a functional simulation [patent_app_type] => utility [patent_app_number] => 16/118442 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5908 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118442
System and method for interactively controlling the course of a functional simulation Aug 30, 2018 Issued
Array ( [id] => 15595011 [patent_doc_number] => 20200074040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => HIERARCHICAL EXPRESSION COVERAGE CLUSTERING FOR DESIGN VERIFICATION [patent_app_type] => utility [patent_app_number] => 16/119921 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119921
HIERARCHICAL EXPRESSION COVERAGE CLUSTERING FOR DESIGN VERIFICATION Aug 30, 2018 Abandoned
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