Search

Aric Lin

Examiner (ID: 5442, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
61
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15501091 [patent_doc_number] => 20200050734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => APPARATUSES HAVING DIVERSIFIED LOGIC CIRCUITS AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/057106 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057106
APPARATUSES HAVING DIVERSIFIED LOGIC CIRCUITS AND METHODS THEREOF Aug 6, 2018 Abandoned
Array ( [id] => 15501083 [patent_doc_number] => 20200050730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => RE-ROUTING TIME CRITICAL MULTI-SINK NETS IN CHIP DESIGN [patent_app_type] => utility [patent_app_number] => 16/056585 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056585
RE-ROUTING TIME CRITICAL MULTI-SINK NETS IN CHIP DESIGN Aug 6, 2018 Abandoned
Array ( [id] => 16802388 [patent_doc_number] => 10997335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Exceptional logic element management [patent_app_type] => utility [patent_app_number] => 16/045199 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 10193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/045199
Exceptional logic element management Jul 24, 2018 Issued
Array ( [id] => 13598457 [patent_doc_number] => 20180350777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/043239 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043239
Semiconductor device Jul 23, 2018 Issued
Array ( [id] => 16802387 [patent_doc_number] => 10997334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Implementing a logic design [patent_app_type] => utility [patent_app_number] => 16/043031 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 38 [patent_no_of_words] => 11050 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043031 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043031
Implementing a logic design Jul 22, 2018 Issued
Array ( [id] => 16248556 [patent_doc_number] => 10747919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Generating path execution times [patent_app_type] => utility [patent_app_number] => 16/042822 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 11302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16042822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/042822
Generating path execution times Jul 22, 2018 Issued
Array ( [id] => 16851249 [patent_doc_number] => 20210151994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => METHOD FOR CHARGING BATTERIES FOR AN AIRCRAFT AND SYSTEM FOR STORING ELECTRICAL ENERGY [patent_app_type] => utility [patent_app_number] => 16/622803 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/622803
METHOD FOR CHARGING BATTERIES FOR AN AIRCRAFT AND SYSTEM FOR STORING ELECTRICAL ENERGY Jun 6, 2018 Abandoned
Array ( [id] => 17062362 [patent_doc_number] => 11106968 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Circuit arrangements and methods for traversing input feature maps [patent_app_type] => utility [patent_app_number] => 15/989075 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989075 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989075
Circuit arrangements and methods for traversing input feature maps May 23, 2018 Issued
Array ( [id] => 16745456 [patent_doc_number] => 10970446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Automated pipeline insertion on a bus [patent_app_type] => utility [patent_app_number] => 15/988448 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5258 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988448
Automated pipeline insertion on a bus May 23, 2018 Issued
Array ( [id] => 16279232 [patent_doc_number] => 10762263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-01 [patent_title] => Searching for values of a bus in digital waveform data [patent_app_type] => utility [patent_app_number] => 15/988293 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7132 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988293
Searching for values of a bus in digital waveform data May 23, 2018 Issued
Array ( [id] => 15182903 [patent_doc_number] => 20190362043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => DYNAMIC UPDATE OF MACRO TIMING MODELS DURING HIGHER-LEVEL TIMING ANALYSIS [patent_app_type] => utility [patent_app_number] => 15/988132 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988132
DYNAMIC UPDATE OF MACRO TIMING MODELS DURING HIGHER-LEVEL TIMING ANALYSIS May 23, 2018 Abandoned
Array ( [id] => 16033113 [patent_doc_number] => 10678980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Combination map based composite design [patent_app_type] => utility [patent_app_number] => 15/974478 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 9640 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974478 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/974478
Combination map based composite design May 7, 2018 Issued
Array ( [id] => 13350541 [patent_doc_number] => 20180226810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SYSTEM AND METHOD FOR BATTERY PACK MANAGEMENT USING PREDICTIVE BALANCING [patent_app_type] => utility [patent_app_number] => 15/946328 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946328
System and method for battery pack management using predictive balancing Apr 4, 2018 Issued
Array ( [id] => 16864903 [patent_doc_number] => 11023647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Integrated circuit stack verification method and system for performing the same [patent_app_type] => utility [patent_app_number] => 15/921040 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/921040
Integrated circuit stack verification method and system for performing the same Mar 13, 2018 Issued
Array ( [id] => 15599343 [patent_doc_number] => 20200076206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => POWER SUPPLY DEVICE [patent_app_type] => utility [patent_app_number] => 16/495696 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16495696 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/495696
Power supply device Jan 28, 2018 Issued
Array ( [id] => 12678643 [patent_doc_number] => 20180118047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SYSTEM AND METHOD FOR ELECTRIC VEHICLE CHARGING ANALYSIS AND FEEDBACK [patent_app_type] => utility [patent_app_number] => 15/851708 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851708 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/851708
SYSTEM AND METHOD FOR ELECTRIC VEHICLE CHARGING ANALYSIS AND FEEDBACK Dec 20, 2017 Abandoned
Array ( [id] => 16179346 [patent_doc_number] => 20200226314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => RECONFIGURABLE INTEGRATED CIRCUIT AND OPERATING PRINCIPLE [patent_app_type] => utility [patent_app_number] => 16/467421 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467421 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/467421
Reconfigurable integrated circuit and operating principle Dec 7, 2017 Issued
Array ( [id] => 17501204 [patent_doc_number] => 11289919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Charging control system [patent_app_type] => utility [patent_app_number] => 16/312764 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5648 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 480 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/312764
Charging control system Dec 7, 2017 Issued
Array ( [id] => 12592536 [patent_doc_number] => 20180089341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => Self Equivalence in Hardware Designs [patent_app_type] => utility [patent_app_number] => 15/831329 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831329 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831329
Self Equivalence in Hardware Designs Dec 3, 2017 Abandoned
Array ( [id] => 14458191 [patent_doc_number] => 10325059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Incremental common path pessimism analysis [patent_app_type] => utility [patent_app_number] => 15/795589 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795589 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795589
Incremental common path pessimism analysis Oct 26, 2017 Issued
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