Search

Aric Lin

Examiner (ID: 5442, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
61
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12666430 [patent_doc_number] => 20180113976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => Flow Control In Networking System-On-Chip Verification [patent_app_type] => utility [patent_app_number] => 15/792078 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792078
Flow control in networking system-on-chip verification Oct 23, 2017 Issued
Array ( [id] => 16217530 [patent_doc_number] => 10733344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Method of selecting a prover [patent_app_type] => utility [patent_app_number] => 15/790339 [patent_app_country] => US [patent_app_date] => 2017-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 9217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790339 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/790339
Method of selecting a prover Oct 22, 2017 Issued
Array ( [id] => 15609889 [patent_doc_number] => 10586008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Removal of artificial resonances using boundary element method [patent_app_type] => utility [patent_app_number] => 15/789719 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789719
Removal of artificial resonances using boundary element method Oct 19, 2017 Issued
Array ( [id] => 16574354 [patent_doc_number] => 10896278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Support method, and information processing apparatus [patent_app_type] => utility [patent_app_number] => 15/789008 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7705 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789008 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789008
Support method, and information processing apparatus Oct 19, 2017 Issued
Array ( [id] => 12689269 [patent_doc_number] => 20180121589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => DEVICE DESIGN SUPPORT METHOD AND DEVICE DESIGN SUPPORT APPARATUS [patent_app_type] => utility [patent_app_number] => 15/788303 [patent_app_country] => US [patent_app_date] => 2017-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788303 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/788303
DEVICE DESIGN SUPPORT METHOD AND DEVICE DESIGN SUPPORT APPARATUS Oct 18, 2017 Abandoned
Array ( [id] => 15642593 [patent_doc_number] => 10594314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Mitigation of simultaneous switching output effects [patent_app_type] => utility [patent_app_number] => 15/785547 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4784 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785547 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785547
Mitigation of simultaneous switching output effects Oct 16, 2017 Issued
Array ( [id] => 16683559 [patent_doc_number] => 10943039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Software-driven design optimization for fixed-point multiply-accumulate circuitry [patent_app_type] => utility [patent_app_number] => 15/786105 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786105 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786105
Software-driven design optimization for fixed-point multiply-accumulate circuitry Oct 16, 2017 Issued
Array ( [id] => 14797471 [patent_doc_number] => 10401737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Process dose and process bias determination for beam lithography [patent_app_type] => utility [patent_app_number] => 15/785785 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7950 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785785
Process dose and process bias determination for beam lithography Oct 16, 2017 Issued
Array ( [id] => 12152929 [patent_doc_number] => 20180024192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'TEST PATTERN COUNT REDUCTION FOR TESTING DELAY FAULTS' [patent_app_type] => utility [patent_app_number] => 15/721511 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14341 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721511 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721511
TEST PATTERN COUNT REDUCTION FOR TESTING DELAY FAULTS Sep 28, 2017 Abandoned
Array ( [id] => 14177979 [patent_doc_number] => 10263011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs [patent_app_type] => utility [patent_app_number] => 15/712723 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1810 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712723 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/712723
Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs Sep 21, 2017 Issued
Array ( [id] => 12457296 [patent_doc_number] => 09984970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-29 [patent_title] => Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs [patent_app_type] => utility [patent_app_number] => 15/712686 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1810 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712686 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/712686
Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs Sep 21, 2017 Issued
Array ( [id] => 17114357 [patent_doc_number] => 20210294954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => INTEGRATED CIRCUIT WITH A DYNAMICS-BASED RECONFIGURABLE LOGIC BLOCK [patent_app_type] => utility [patent_app_number] => 16/326603 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16326603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/326603
Integrated circuit with a dynamics-based reconfigurable logic block Aug 28, 2017 Issued
Array ( [id] => 15789631 [patent_doc_number] => 10628542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Core-only system management interrupt [patent_app_type] => utility [patent_app_number] => 15/640532 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 19746 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640532 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640532
Core-only system management interrupt Jun 30, 2017 Issued
Array ( [id] => 13783283 [patent_doc_number] => 20190005180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => Integrated Circuit Layouts with Fill Feature Shapes [patent_app_type] => utility [patent_app_number] => 15/637484 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15637484 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/637484
Integrated circuit layouts with fill feature shapes Jun 28, 2017 Issued
Array ( [id] => 17637201 [patent_doc_number] => 11347925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Power grid architecture and optimization with EUV lithography [patent_app_type] => utility [patent_app_number] => 15/636278 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636278
Power grid architecture and optimization with EUV lithography Jun 27, 2017 Issued
Array ( [id] => 12689281 [patent_doc_number] => 20180121593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => VERTICAL TRANSISTORS WITH MERGED ACTIVE AREA REGIONS [patent_app_type] => utility [patent_app_number] => 15/589504 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589504 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589504
VERTICAL TRANSISTORS WITH MERGED ACTIVE AREA REGIONS May 7, 2017 Abandoned
Array ( [id] => 12692878 [patent_doc_number] => 20180122792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => VERTICAL TRANSISTORS WITH MERGED ACTIVE AREA REGIONS [patent_app_type] => utility [patent_app_number] => 15/439148 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/439148
VERTICAL TRANSISTORS WITH MERGED ACTIVE AREA REGIONS Feb 21, 2017 Abandoned
Array ( [id] => 18046288 [patent_doc_number] => 11520239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Separation of contributions to metrology data [patent_app_type] => utility [patent_app_number] => 16/075696 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 24586 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16075696 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/075696
Separation of contributions to metrology data Feb 16, 2017 Issued
Array ( [id] => 11824031 [patent_doc_number] => 20170212968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'Circuit Verification' [patent_app_type] => utility [patent_app_number] => 15/405328 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/405328
Circuit Verification Jan 12, 2017 Abandoned
Array ( [id] => 13085193 [patent_doc_number] => 10062669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/393706 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 11017 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393706 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393706
Semiconductor device Dec 28, 2016 Issued
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