Search

Aric Lin

Examiner (ID: 5442, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
61
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11103035 [patent_doc_number] => 20160300005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'CELL LAYOUT UTILIZING BOUNDARY CELL WITH MIXED POLY PITCH WITHIN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/081936 [patent_app_country] => US [patent_app_date] => 2016-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081936
Cell layout utilizing boundary cell with mixed poly pitch within integrated circuit Mar 26, 2016 Issued
Array ( [id] => 11086677 [patent_doc_number] => 20160283643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION' [patent_app_type] => utility [patent_app_number] => 15/081291 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081291
System and method of analyzing integrated circuit in consideration of a process variation Mar 24, 2016 Issued
Array ( [id] => 14556237 [patent_doc_number] => 10346580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Checking wafer-level integrated designs for rule compliance [patent_app_type] => utility [patent_app_number] => 15/081226 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5328 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081226
Checking wafer-level integrated designs for rule compliance Mar 24, 2016 Issued
Array ( [id] => 16146263 [patent_doc_number] => 10706203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Method and apparatus for verifying initial state equivalence of changed registers in retimed circuits [patent_app_type] => utility [patent_app_number] => 15/079518 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15804 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15079518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/079518
Method and apparatus for verifying initial state equivalence of changed registers in retimed circuits Mar 23, 2016 Issued
Array ( [id] => 10816466 [patent_doc_number] => 20160162626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'LITHOGRAPHY PROCESS WINDOW PREDICTION BASED ON DESIGN DATA' [patent_app_type] => utility [patent_app_number] => 15/042779 [patent_app_country] => US [patent_app_date] => 2016-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8869 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/042779
LITHOGRAPHY PROCESS WINDOW PREDICTION BASED ON DESIGN DATA Feb 11, 2016 Abandoned
Array ( [id] => 11839006 [patent_doc_number] => 20170220726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHOD AND SYSTEM FOR PERFORMING A DESIGN SPACE EXPLORATION OF A CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/010814 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15010814 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/010814
METHOD AND SYSTEM FOR PERFORMING A DESIGN SPACE EXPLORATION OF A CIRCUIT Jan 28, 2016 Abandoned
Array ( [id] => 15059527 [patent_doc_number] => 10460070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Optimized electromigration analysis [patent_app_type] => utility [patent_app_number] => 15/008546 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008546
Optimized electromigration analysis Jan 27, 2016 Issued
Array ( [id] => 14490099 [patent_doc_number] => 10331840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Resource aware method for optimizing wires for slew, slack, or noise [patent_app_type] => utility [patent_app_number] => 14/996402 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14996402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/996402
Resource aware method for optimizing wires for slew, slack, or noise Jan 14, 2016 Issued
Array ( [id] => 11070241 [patent_doc_number] => 20160267205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'Systems, Methods and Computer Program Products for Analyzing Performance of Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 14/991124 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5606 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991124 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/991124
Systems, methods and computer program products for analyzing performance of semiconductor devices Jan 7, 2016 Issued
Array ( [id] => 11709274 [patent_doc_number] => 20170177773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'METHOD FOR TRANSLATING DOMAIN-SPECIFIC FUNCTIONAL MODELS TO SIMULATION MODELS' [patent_app_type] => utility [patent_app_number] => 14/970569 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970569 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/970569
METHOD FOR TRANSLATING DOMAIN-SPECIFIC FUNCTIONAL MODELS TO SIMULATION MODELS Dec 15, 2015 Abandoned
Array ( [id] => 11709276 [patent_doc_number] => 20170177776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'PARTITIONING OF WIRING FOR CAPACITANCE EXTRACTION WITHOUT LOSS IN ACCURACY' [patent_app_type] => utility [patent_app_number] => 14/970745 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970745 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/970745
PARTITIONING OF WIRING FOR CAPACITANCE EXTRACTION WITHOUT LOSS IN ACCURACY Dec 15, 2015 Abandoned
Array ( [id] => 13227125 [patent_doc_number] => 10127338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information [patent_app_type] => utility [patent_app_number] => 14/969647 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969647 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969647
System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information Dec 14, 2015 Issued
Array ( [id] => 11693432 [patent_doc_number] => 20170169149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SYSTEM DESIGN USING ACCURATE PERFORMANCE MODELS' [patent_app_type] => utility [patent_app_number] => 14/970072 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970072 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/970072
System design using accurate performance models Dec 14, 2015 Issued
Array ( [id] => 12512712 [patent_doc_number] => 10001698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Layout hierachical structure defined in polar coordinate [patent_app_type] => utility [patent_app_number] => 14/969182 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969182 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969182
Layout hierachical structure defined in polar coordinate Dec 14, 2015 Issued
Array ( [id] => 14331331 [patent_doc_number] => 10296686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Switching-activity-based selection of low-power sequential circuitry [patent_app_type] => utility [patent_app_number] => 14/968022 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5971 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968022 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968022
Switching-activity-based selection of low-power sequential circuitry Dec 13, 2015 Issued
Array ( [id] => 11028507 [patent_doc_number] => 20160225464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'DESIGNING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/968116 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6057 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968116
Designing method of semiconductor device and semiconductor device Dec 13, 2015 Issued
Array ( [id] => 11693439 [patent_doc_number] => 20170169156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'Designing a Density Driven Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 14/967626 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967626 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967626
Designing a density driven integrated circuit Dec 13, 2015 Issued
Array ( [id] => 12951334 [patent_doc_number] => 09836572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Incremental common path pessimism analysis [patent_app_type] => utility [patent_app_number] => 14/946043 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5260 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946043
Incremental common path pessimism analysis Nov 18, 2015 Issued
Array ( [id] => 11352678 [patent_doc_number] => 20160371418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'ROUTING OF NETS OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/941579 [patent_app_country] => US [patent_app_date] => 2015-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7256 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941579 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941579
Routing of nets of an integrated circuit Nov 13, 2015 Issued
Array ( [id] => 10771266 [patent_doc_number] => 20160117422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'REGION-BASED SYNTHESIS OF LOGIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/862567 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3616 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862567 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862567
REGION-BASED SYNTHESIS OF LOGIC CIRCUITS Sep 22, 2015 Abandoned
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