Search

Aric Lin

Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
60
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12496095 [patent_doc_number] => 09996650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Modeling the performance of a field effect transistor having a dynamically depleted channel region [patent_app_type] => utility [patent_app_number] => 14/660334 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14564 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 627 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660334 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660334
Modeling the performance of a field effect transistor having a dynamically depleted channel region Mar 16, 2015 Issued
Array ( [id] => 11078264 [patent_doc_number] => 20160275227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'OPTIMIZING INTERCONNECT DESIGNS IN LOW-POWER INTEGRATED CIRCUITS (ICs)' [patent_app_type] => utility [patent_app_number] => 14/658504 [patent_app_country] => US [patent_app_date] => 2015-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14658504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/658504
OPTIMIZING INTERCONNECT DESIGNS IN LOW-POWER INTEGRATED CIRCUITS (ICs) Mar 15, 2015 Abandoned
Array ( [id] => 13120733 [patent_doc_number] => 10078720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Methods and systems for circuit fault diagnosis [patent_app_type] => utility [patent_app_number] => 14/656834 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656834 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656834
Methods and systems for circuit fault diagnosis Mar 12, 2015 Issued
Array ( [id] => 10512324 [patent_doc_number] => 09239902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-19 [patent_title] => 'Method of preparing a layout and system for performing the same' [patent_app_type] => utility [patent_app_number] => 14/625959 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/625959
Method of preparing a layout and system for performing the same Feb 18, 2015 Issued
Array ( [id] => 10349973 [patent_doc_number] => 20150234978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Cell Internal Defect Diagnosis' [patent_app_type] => utility [patent_app_number] => 14/621868 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/621868
Cell Internal Defect Diagnosis Feb 12, 2015 Abandoned
Array ( [id] => 11042643 [patent_doc_number] => 20160239599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'LAYOUT CHECKING METHOD FOR ADVANCED DOUBLE PATTERNING PHOTOLITHOGRAPHY WITH MULTIPLE SPACING CRITERIA' [patent_app_type] => utility [patent_app_number] => 14/622009 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622009
Layout checking method for advanced double patterning photolithography with multiple spacing criteria Feb 12, 2015 Issued
Array ( [id] => 11042642 [patent_doc_number] => 20160239598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/621054 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/621054
Integrated circuit stack verification method and system for performing the same Feb 11, 2015 Issued
Array ( [id] => 11501842 [patent_doc_number] => 20170076027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM WHEREIN INFORMATION PROCESSING PROGRAM IS STORED' [patent_app_type] => utility [patent_app_number] => 15/122706 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5176 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15122706 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/122706
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM WHEREIN INFORMATION PROCESSING PROGRAM IS STORED Jan 19, 2015 Abandoned
Array ( [id] => 10824973 [patent_doc_number] => 20160171140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'METHOD AND SYSTEM FOR DETERMINING MINIMUM OPERATIONAL VOLTAGE FOR TRANSISTOR MEMORY-BASED DEVICES' [patent_app_type] => utility [patent_app_number] => 14/567634 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567634 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567634
METHOD AND SYSTEM FOR DETERMINING MINIMUM OPERATIONAL VOLTAGE FOR TRANSISTOR MEMORY-BASED DEVICES Dec 10, 2014 Abandoned
Array ( [id] => 11585010 [patent_doc_number] => 09639654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/567569 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8075 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567569 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567569
Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit Dec 10, 2014 Issued
Array ( [id] => 10808764 [patent_doc_number] => 20160154922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'OPTICAL PROXIMITY CORRECTION TAKING INTO ACCOUNT WAFER TOPOGRAPHY' [patent_app_type] => utility [patent_app_number] => 14/556711 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6167 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14556711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/556711
OPTICAL PROXIMITY CORRECTION TAKING INTO ACCOUNT WAFER TOPOGRAPHY Nov 30, 2014 Abandoned
Array ( [id] => 10801771 [patent_doc_number] => 20160147928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT LAYOUT GENERATION' [patent_app_type] => utility [patent_app_number] => 14/555191 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555191 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555191
Method, device and computer program product for integrated circuit layout generation Nov 25, 2014 Issued
Array ( [id] => 10771277 [patent_doc_number] => 20160117433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/525320 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525320 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/525320
INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION Oct 27, 2014 Abandoned
Array ( [id] => 10771265 [patent_doc_number] => 20160117421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'REGION-BASED SYNTHESIS OF LOGIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/525598 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3585 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525598 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/525598
REGION-BASED SYNTHESIS OF LOGIC CIRCUITS Oct 27, 2014 Abandoned
Array ( [id] => 10771275 [patent_doc_number] => 20160117432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'METHOD AND APPARATUS FOR ASSISTED METAL ROUTING' [patent_app_type] => utility [patent_app_number] => 14/523558 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523558 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/523558
Method and apparatus for assisted metal routing Oct 23, 2014 Issued
Array ( [id] => 10284822 [patent_doc_number] => 20150169820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'WEAK POINTS AUTO-CORRECTION PROCESS FOR OPC TAPE-OUT' [patent_app_type] => utility [patent_app_number] => 14/502986 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5203 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502986 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502986
WEAK POINTS AUTO-CORRECTION PROCESS FOR OPC TAPE-OUT Sep 29, 2014 Abandoned
Array ( [id] => 10576219 [patent_doc_number] => 09298866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Method and system for modeling a flip-flop of a user design' [patent_app_type] => utility [patent_app_number] => 14/501699 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501699
Method and system for modeling a flip-flop of a user design Sep 29, 2014 Issued
Array ( [id] => 11775379 [patent_doc_number] => 09384310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-05 [patent_title] => 'View data sharing for efficient multi-mode multi-corner timing analysis' [patent_app_type] => utility [patent_app_number] => 14/502611 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3389 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502611 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502611
View data sharing for efficient multi-mode multi-corner timing analysis Sep 29, 2014 Issued
Array ( [id] => 11049956 [patent_doc_number] => 20160246915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'Estimation Of Effective Channel Length for Finfets and Nano-wires' [patent_app_type] => utility [patent_app_number] => 15/024009 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7073 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15024009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/024009
Estimation of effective channel length for FinFETs and nano-wires Sep 25, 2014 Issued
Array ( [id] => 12416634 [patent_doc_number] => 09972491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Mask data generation method, mask data generation system, and recording medium [patent_app_type] => utility [patent_app_number] => 14/476945 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 10609 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476945 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/476945
Mask data generation method, mask data generation system, and recording medium Sep 3, 2014 Issued
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