Search

Aric Lin

Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
60
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18470807 [patent_doc_number] => 20230205093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD OF MANUFACTURING PHOTO MASKS [patent_app_type] => utility [patent_app_number] => 18/114845 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/114845
METHOD OF MANUFACTURING PHOTO MASKS Feb 26, 2023 Abandoned
Array ( [id] => 18599268 [patent_doc_number] => 20230274068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => PERFORMING NON-PREFERRED DIRECTION DETAILED ROUTING FOLLOWED BY PREFERRED DIRECTION GLOBAL AND DETAILED ROUTING [patent_app_type] => utility [patent_app_number] => 18/110338 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110338
PERFORMING NON-PREFERRED DIRECTION DETAILED ROUTING FOLLOWED BY PREFERRED DIRECTION GLOBAL AND DETAILED ROUTING Feb 14, 2023 Pending
Array ( [id] => 18599269 [patent_doc_number] => 20230274069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => INTEGRATED CIRCUIT DESIGN WITH NON-PREFERRED DIRECTION CURVILINEAR WIRING [patent_app_type] => utility [patent_app_number] => 18/110334 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110334 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110334
INTEGRATED CIRCUIT DESIGN WITH NON-PREFERRED DIRECTION CURVILINEAR WIRING Feb 14, 2023 Pending
Array ( [id] => 18584396 [patent_doc_number] => 20230266659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => OPC Method [patent_app_type] => utility [patent_app_number] => 18/154154 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154154 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154154
OPC Method Jan 12, 2023 Pending
Array ( [id] => 18499520 [patent_doc_number] => 20230222277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => MARGIN CALIBRATION METHOD AND MARGIN CALIBRATION SYSTEM FOR STATIC TIMING ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/150767 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150767
MARGIN CALIBRATION METHOD AND MARGIN CALIBRATION SYSTEM FOR STATIC TIMING ANALYSIS Jan 4, 2023 Pending
Array ( [id] => 18957687 [patent_doc_number] => 20240046014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => PROCESS TO RELAY KNOWLEDGE AND GUIDE SYNTHESIS ALONGSIDE EARLY DETECTION OF LOGIC OPTIMIZATIONS [patent_app_type] => utility [patent_app_number] => 18/071396 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/071396
PROCESS TO RELAY KNOWLEDGE AND GUIDE SYNTHESIS ALONGSIDE EARLY DETECTION OF LOGIC OPTIMIZATIONS Nov 28, 2022 Pending
Array ( [id] => 18258067 [patent_doc_number] => 20230085107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => VERIFYING A HARDWARE DESIGN FOR A MULTI-STAGE COMPONENT [patent_app_type] => utility [patent_app_number] => 17/990518 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990518
Verifying a hardware design for a multi-stage component Nov 17, 2022 Issued
Array ( [id] => 20667653 [patent_doc_number] => 12609435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Filter manufacturing method and filter manufactured by the method [patent_app_type] => utility [patent_app_number] => 17/977308 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 1118 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/977308
Filter manufacturing method and filter manufactured by the method Oct 30, 2022 Issued
Array ( [id] => 18182030 [patent_doc_number] => 20230042759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => SEPARATION OF CONTRIBUTIONS TO METROLOGY DATA [patent_app_type] => utility [patent_app_number] => 17/968352 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/968352
SEPARATION OF CONTRIBUTIONS TO METROLOGY DATA Oct 17, 2022 Pending
Array ( [id] => 18223212 [patent_doc_number] => 20230062206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DETERMINING SUBSTRATE PROFILE PROPERTIES USING MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 18/046872 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046872
DETERMINING SUBSTRATE PROFILE PROPERTIES USING MACHINE LEARNING Oct 13, 2022 Pending
Array ( [id] => 18925798 [patent_doc_number] => 20240028802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => AUTOMATIC LOW LEVEL OPERATOR LOOP GENERATION, PARALLELIZATION AND VECTORIZATION FOR TENSOR COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 17/964085 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17964085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/964085
Automatic low level operator loop generation, parallelization and vectorization for tensor computations Oct 11, 2022 Issued
Array ( [id] => 18209268 [patent_doc_number] => 20230055528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SYSTEMS AND METHODS FOR EXECUTING A PROGRAMMABLE FINITE STATE MACHINE THAT ACCELERATES FETCHLESS COMPUTATIONS AND OPERATIONS OF AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/953312 [patent_app_country] => US [patent_app_date] => 2022-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953312
Systems and methods for executing a programmable finite state machine that accelerates fetchless computations and operations of an array of processing cores of an integrated circuit Sep 25, 2022 Issued
Array ( [id] => 19069851 [patent_doc_number] => 20240104277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SINGLE CORNER MIXED VOLTAGE NOISE IMPACT ON FUNCTION ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/934239 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934239
Single corner mixed voltage noise impact on function analysis Sep 21, 2022 Issued
Array ( [id] => 18393720 [patent_doc_number] => 20230161940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => ZERO DIFFUSION BREAK [patent_app_type] => utility [patent_app_number] => 17/863382 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863382 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863382
ZERO DIFFUSION BREAK Jul 11, 2022 Pending
Array ( [id] => 18422006 [patent_doc_number] => 20230176470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => METHOD OF GENERATING CURVE SUB-RESOLUTION ASSIST FEATURE (SRAF), METHOD OF VERIFYING MASK RULE CHECK (MRC), AND METHOD OF MANUFACTURING MASK INCLUDING METHOD OF GENERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/860139 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860139
METHOD OF GENERATING CURVE SUB-RESOLUTION ASSIST FEATURE (SRAF), METHOD OF VERIFYING MASK RULE CHECK (MRC), AND METHOD OF MANUFACTURING MASK INCLUDING METHOD OF GENERATING THE SAME Jul 7, 2022 Pending
Array ( [id] => 18811160 [patent_doc_number] => 20230385496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => LOGIC LOCKING OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/664861 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664861
LOGIC LOCKING OPERATIONS May 23, 2022 Pending
Array ( [id] => 20175011 [patent_doc_number] => 12393759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Integrated circuit layouts with fill feature shapes [patent_app_type] => utility [patent_app_number] => 17/745224 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745224
Integrated circuit layouts with fill feature shapes May 15, 2022 Issued
Array ( [id] => 18713389 [patent_doc_number] => 20230336025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => CONDUCTOR ROUTING IN HIGH ENERGY WIRELESS POWER TRANSFER PADS [patent_app_type] => utility [patent_app_number] => 17/723378 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723378
Conductor routing in high energy wireless power transfer pads Apr 17, 2022 Issued
Array ( [id] => 17932145 [patent_doc_number] => 20220327270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => METHOD, SYSTEM, MEDIUM, AND PROGRAM PRODUCT FOR PATH VERIFICATION IN LOGIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/709186 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709186
METHOD, SYSTEM, MEDIUM, AND PROGRAM PRODUCT FOR PATH VERIFICATION IN LOGIC CIRCUIT Mar 29, 2022 Pending
Array ( [id] => 17722424 [patent_doc_number] => 20220215146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD FOR RECOGNIZING ANALOG CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/701095 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701095
METHOD FOR RECOGNIZING ANALOG CIRCUIT STRUCTURE Mar 21, 2022 Abandoned
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