
Aric Lin
Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 612 |
| Issued Applications | 347 |
| Pending Applications | 60 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9137380
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[patent_title] => 'METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 13/875263
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Array
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[patent_issue_date] => 2015-03-31
[patent_title] => 'Method for input/output design of chip'
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Array
(
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[patent_title] => 'SEMICONDUCTOR DEVICE'
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Array
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[patent_issue_date] => 2016-11-22
[patent_title] => 'Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language'
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Array
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Array
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[patent_title] => 'CUTTER IN DIAGNOSIS (CID) A METHOD TO IMPROVE THE THROUGHPUT OF THE YIELD RAMP UP PROCESS'
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Array
(
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[patent_title] => 'Method for Forming Photo-masks and OPC Method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/802833 | Method for Forming Photo-masks and OPC Method | Mar 13, 2013 | Abandoned |
Array
(
[id] => 9071307
[patent_doc_number] => 20130263063
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[patent_issue_date] => 2013-10-03
[patent_title] => 'MASK DESIGN METHOD, PROGRAM, AND MASK DESIGN SYSTEM'
[patent_app_type] => utility
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Array
(
[id] => 9071315
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[patent_issue_date] => 2013-10-03
[patent_title] => 'APPARATUS AND METHOD TO COLLECT AND CONDENSE DESIGN VIOLATIONS FROM OUTPUT DATA FILES'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/774963 | Apparatus and method to collect and condense design violations from output data files | Feb 21, 2013 | Issued |
Array
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[id] => 8961343
[patent_doc_number] => 20130200945
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[patent_kind] => A1
[patent_issue_date] => 2013-08-08
[patent_title] => 'STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN'
[patent_app_type] => utility
[patent_app_number] => 13/757617
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/757617 | STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN | Jan 31, 2013 | Abandoned |
Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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