Search

Aric Lin

Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
60
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9137380 [patent_doc_number] => 20130298095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/875263 [patent_app_country] => US [patent_app_date] => 2013-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2657 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13875263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/875263
METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM Apr 30, 2013 Abandoned
Array ( [id] => 9947703 [patent_doc_number] => 08997032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Method for input/output design of chip' [patent_app_type] => utility [patent_app_number] => 13/863503 [patent_app_country] => US [patent_app_date] => 2013-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6129 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13863503 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/863503
Method for input/output design of chip Apr 15, 2013 Issued
Array ( [id] => 9118133 [patent_doc_number] => 20130285055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/857692 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11420 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857692 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857692
Semiconductor device Apr 4, 2013 Issued
Array ( [id] => 11285737 [patent_doc_number] => 09501592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-22 [patent_title] => 'Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language' [patent_app_type] => utility [patent_app_number] => 13/831943 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 15080 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831943 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831943
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language Mar 14, 2013 Issued
Array ( [id] => 11179919 [patent_doc_number] => 09411912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Clock topology planning for reduced power consumption' [patent_app_type] => utility [patent_app_number] => 13/844683 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 68 [patent_no_of_words] => 31202 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844683
Clock topology planning for reduced power consumption Mar 14, 2013 Issued
Array ( [id] => 9746608 [patent_doc_number] => 20140282327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'CUTTER IN DIAGNOSIS (CID) A METHOD TO IMPROVE THE THROUGHPUT OF THE YIELD RAMP UP PROCESS' [patent_app_type] => utility [patent_app_number] => 13/830683 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13830683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/830683
CUTTER IN DIAGNOSIS (CID) A METHOD TO IMPROVE THE THROUGHPUT OF THE YIELD RAMP UP PROCESS Mar 13, 2013 Abandoned
Array ( [id] => 9746576 [patent_doc_number] => 20140282295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Method for Forming Photo-masks and OPC Method' [patent_app_type] => utility [patent_app_number] => 13/802833 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13802833 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/802833
Method for Forming Photo-masks and OPC Method Mar 13, 2013 Abandoned
Array ( [id] => 9071307 [patent_doc_number] => 20130263063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'MASK DESIGN METHOD, PROGRAM, AND MASK DESIGN SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/795513 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8692 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795513
Mask design method, program, and mask design system Mar 11, 2013 Issued
Array ( [id] => 9071315 [patent_doc_number] => 20130263071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'APPARATUS AND METHOD TO COLLECT AND CONDENSE DESIGN VIOLATIONS FROM OUTPUT DATA FILES' [patent_app_type] => utility [patent_app_number] => 13/774963 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774963 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774963
Apparatus and method to collect and condense design violations from output data files Feb 21, 2013 Issued
Array ( [id] => 8961343 [patent_doc_number] => 20130200945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN' [patent_app_type] => utility [patent_app_number] => 13/757617 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757617 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757617
STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN Jan 31, 2013 Abandoned
Array ( [id] => 10644544 [patent_doc_number] => 09361416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Dynamic reconfiguration of programmable hardware' [patent_app_type] => utility [patent_app_number] => 13/994882 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 17024 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994882 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994882
Dynamic reconfiguration of programmable hardware Jan 29, 2013 Issued
Array ( [id] => 10854356 [patent_doc_number] => 08881067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Method and apparatus for monitoring cross-sectional shape of a pattern formed on a semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/738795 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 57 [patent_no_of_words] => 25080 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738795 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/738795
Method and apparatus for monitoring cross-sectional shape of a pattern formed on a semiconductor device Jan 9, 2013 Issued
Array ( [id] => 9012614 [patent_doc_number] => 08527935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-03 [patent_title] => 'System for reducing power consumption of electronic circuit' [patent_app_type] => utility [patent_app_number] => 13/735049 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735049 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735049
System for reducing power consumption of electronic circuit Jan 6, 2013 Issued
Array ( [id] => 9326354 [patent_doc_number] => 08661391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Spare cell insertion based on reachable state analysis' [patent_app_type] => utility [patent_app_number] => 13/732989 [patent_app_country] => US [patent_app_date] => 2013-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4749 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732989 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/732989
Spare cell insertion based on reachable state analysis Jan 1, 2013 Issued
Array ( [id] => 9717333 [patent_doc_number] => 20140253031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'WIRELESS BATTERY CHARGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/349881 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3792 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14349881 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/349881
WIRELESS BATTERY CHARGING SYSTEM Oct 7, 2012 Abandoned
Array ( [id] => 9386390 [patent_doc_number] => 20140089873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'Automatically Identifying Resettable Flops For Digital Designs' [patent_app_type] => utility [patent_app_number] => 13/627653 [patent_app_country] => US [patent_app_date] => 2012-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5379 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13627653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/627653
Automatically identifying resettable flops for digital designs Sep 25, 2012 Issued
Array ( [id] => 9940917 [patent_doc_number] => 08990749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Method and apparatus for optimizing memory-built-in-self test' [patent_app_type] => utility [patent_app_number] => 13/625733 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625733
Method and apparatus for optimizing memory-built-in-self test Sep 23, 2012 Issued
Array ( [id] => 11552106 [patent_doc_number] => 09620971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Battery charger' [patent_app_type] => utility [patent_app_number] => 14/349747 [patent_app_country] => US [patent_app_date] => 2012-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4307 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14349747 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/349747
Battery charger Sep 18, 2012 Issued
Array ( [id] => 9367896 [patent_doc_number] => 20140077769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING CYCLE LIFE CAPACITY OF A BATTERY PACK' [patent_app_type] => utility [patent_app_number] => 13/621907 [patent_app_country] => US [patent_app_date] => 2012-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13621907 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/621907
Method and apparatus for improving cycle life capacity of a battery pack Sep 17, 2012 Issued
Array ( [id] => 10132596 [patent_doc_number] => 09166442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-20 [patent_title] => 'Adaptive input current limiting for switch-mode chargers' [patent_app_type] => utility [patent_app_number] => 13/621447 [patent_app_country] => US [patent_app_date] => 2012-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4856 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13621447 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/621447
Adaptive input current limiting for switch-mode chargers Sep 16, 2012 Issued
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