Search

Aric Lin

Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
60
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7653278 [patent_doc_number] => 20110302547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD AND APPARATUS FOR USING SCENARIO REDUCTION IN A CIRCUIT DESIGN FLOW' [patent_app_type] => utility [patent_app_number] => 12/795596 [patent_app_country] => US [patent_app_date] => 2010-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11696 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302547.pdf [firstpage_image] =>[orig_patent_app_number] => 12795596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/795596
Performing scenario reduction in a circuit design flow Jun 6, 2010 Issued
Array ( [id] => 8878895 [patent_doc_number] => 08473880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-25 [patent_title] => 'Synchronization of parallel memory accesses in a dataflow circuit' [patent_app_type] => utility [patent_app_number] => 12/791256 [patent_app_country] => US [patent_app_date] => 2010-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5875 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12791256 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791256
Synchronization of parallel memory accesses in a dataflow circuit May 31, 2010 Issued
Array ( [id] => 9458724 [patent_doc_number] => 08719751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Simultaneous switching noise analysis' [patent_app_type] => utility [patent_app_number] => 12/789356 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789356 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789356
Simultaneous switching noise analysis May 26, 2010 Issued
Array ( [id] => 6561134 [patent_doc_number] => 20100233877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Method of disposing dummy pattern' [patent_app_type] => utility [patent_app_number] => 12/801114 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9493 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20100233877.pdf [firstpage_image] =>[orig_patent_app_number] => 12801114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801114
Method of disposing dummy pattern May 23, 2010 Abandoned
Array ( [id] => 7569409 [patent_doc_number] => 20110289472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'LAYOUT QUALITY EVALUATION' [patent_app_type] => utility [patent_app_number] => 12/782926 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5154 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289472.pdf [firstpage_image] =>[orig_patent_app_number] => 12782926 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782926
LAYOUT QUALITY EVALUATION May 18, 2010 Abandoned
Array ( [id] => 6652469 [patent_doc_number] => 20100229148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING' [patent_app_type] => utility [patent_app_number] => 12/781887 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7501 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229148.pdf [firstpage_image] =>[orig_patent_app_number] => 12781887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781887
METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING May 17, 2010 Abandoned
Array ( [id] => 10854373 [patent_doc_number] => 08881084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'FinFET boundary optimization' [patent_app_type] => utility [patent_app_number] => 12/780426 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12780426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/780426
FinFET boundary optimization May 13, 2010 Issued
Array ( [id] => 7563099 [patent_doc_number] => 20110276933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Method for Supporting Multiple Libraries Characterized at Different Process, Voltage, and Temperature Points' [patent_app_type] => utility [patent_app_number] => 12/774766 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276933.pdf [firstpage_image] =>[orig_patent_app_number] => 12774766 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774766
Method for supporting multiple libraries characterized at different process, voltage and temperature points May 5, 2010 Issued
Array ( [id] => 6464939 [patent_doc_number] => 20100281448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'LOW-POWER FPGA CIRCUITS AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/773686 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 44474 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281448.pdf [firstpage_image] =>[orig_patent_app_number] => 12773686 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773686
Low-power FPGA circuits and methods May 3, 2010 Issued
Array ( [id] => 6464991 [patent_doc_number] => 20100281452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'LAYOUT DESIGN METHOD, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/767186 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6557 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281452.pdf [firstpage_image] =>[orig_patent_app_number] => 12767186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767186
LAYOUT DESIGN METHOD, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN APPARATUS Apr 25, 2010 Abandoned
Array ( [id] => 6410591 [patent_doc_number] => 20100180253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'DEFECT PATTERN MATCHING AND VERIFICATION IN INTEGRATED CIRCUIT DESIGN AND MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 12/748401 [patent_app_country] => US [patent_app_date] => 2010-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180253.pdf [firstpage_image] =>[orig_patent_app_number] => 12748401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748401
DEFECT PATTERN MATCHING AND VERIFICATION IN INTEGRATED CIRCUIT DESIGN AND MANUFACTURING Mar 26, 2010 Abandoned
Array ( [id] => 6410562 [patent_doc_number] => 20100180250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING LAYOUT REGIONS WITH LOCAL PREFERRED DIRECTIONS' [patent_app_type] => utility [patent_app_number] => 12/731078 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10152 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180250.pdf [firstpage_image] =>[orig_patent_app_number] => 12731078 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731078
Method and apparatus for generating layout regions with local preferred directions Mar 23, 2010 Issued
Array ( [id] => 6366658 [patent_doc_number] => 20100088257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Systems and Methods for Generating Predicates and Assertions' [patent_app_type] => utility [patent_app_number] => 12/634586 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5528 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20100088257.pdf [firstpage_image] =>[orig_patent_app_number] => 12634586 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/634586
Systems and Methods for Generating Predicates and Assertions Dec 8, 2009 Abandoned
Array ( [id] => 6554675 [patent_doc_number] => 20100125821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'Design support method' [patent_app_type] => utility [patent_app_number] => 12/588919 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9061 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20100125821.pdf [firstpage_image] =>[orig_patent_app_number] => 12588919 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588919
Design support method Nov 1, 2009 Abandoned
Array ( [id] => 6619516 [patent_doc_number] => 20100050142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'SPECIAL ENGINEERING CHANGE ORDER CELLS' [patent_app_type] => utility [patent_app_number] => 12/608469 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20100050142.pdf [firstpage_image] =>[orig_patent_app_number] => 12608469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608469
Special engineering change order cells Oct 28, 2009 Issued
Array ( [id] => 8472875 [patent_doc_number] => 08302067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Pin-out designation method for package-board codesign' [patent_app_type] => utility [patent_app_number] => 12/581259 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 6463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12581259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581259
Pin-out designation method for package-board codesign Oct 18, 2009 Issued
Array ( [id] => 9500247 [patent_doc_number] => 08739088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Using constraints wtihin a high-level modeling system for circuit design' [patent_app_type] => utility [patent_app_number] => 12/581104 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 8580 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12581104 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581104
Using constraints wtihin a high-level modeling system for circuit design Oct 15, 2009 Issued
Array ( [id] => 6466018 [patent_doc_number] => 20100146470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'METHOD AND SYSTEM FOR VOLTAGE FLUCTUATION AMOUNT CALCULATION' [patent_app_type] => utility [patent_app_number] => 12/580829 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5655 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146470.pdf [firstpage_image] =>[orig_patent_app_number] => 12580829 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580829
Method and system for voltage fluctuation amount calculation Oct 15, 2009 Issued
Array ( [id] => 6131629 [patent_doc_number] => 20110088008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/579159 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7917 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20110088008.pdf [firstpage_image] =>[orig_patent_app_number] => 12579159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579159
METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR Oct 13, 2009 Abandoned
Array ( [id] => 6154301 [patent_doc_number] => 20110023001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'DYNAMIC RULE CHECKING IN ELECTRONIC DESIGN AUTOMATION' [patent_app_type] => utility [patent_app_number] => 12/579309 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4449 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20110023001.pdf [firstpage_image] =>[orig_patent_app_number] => 12579309 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579309
Dynamic rule checking in electronic design automation Oct 13, 2009 Issued
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