Aric Lin

Array ( [id] => 4678398 [patent_doc_number] => 20080216029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'METHOD AND SYSTEM FOR PERFORMING TARGET ENLARGEMENT IN THE PRESENCE OF CONSTRAINTS' [patent_app_type] => utility [patent_app_number] => 12/036093 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8676 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216029.pdf [firstpage_image] =>[orig_patent_app_number] => 12036093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9326343 [patent_doc_number] => 08661380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Method and apparatus for performing parallel synthesis on a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 12/070478 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7715 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12070478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8120431 [patent_doc_number] => 08161439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Method and apparatus for processing assertions in assertion-based verification of a logic design' [patent_app_type] => utility [patent_app_number] => 12/028909 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161439.pdf [firstpage_image] =>[orig_patent_app_number] => 12028909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5381537 [patent_doc_number] => 20090193376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS' [patent_app_type] => utility [patent_app_number] => 12/022849 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193376.pdf [firstpage_image] =>[orig_patent_app_number] => 12022849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722877 [patent_doc_number] => 20080244486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'INTEGRATED CIRCUIT GENERATING DEVICE, METHOD THEREFOR, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/019249 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 12158 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244486.pdf [firstpage_image] =>[orig_patent_app_number] => 12019249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5356533 [patent_doc_number] => 20090187877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'MULTI-PASS, CONSTRAINED PHASE ASSIGNMENT FOR ALTERNATING PHASE-SHIFT LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 12/017699 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6277 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187877.pdf [firstpage_image] =>[orig_patent_app_number] => 12017699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4700289 [patent_doc_number] => 20080222473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'TEST PATTERN GENERATING DEVICE AND TEST PATTERN GENERATING METHOD' [patent_app_type] => utility [patent_app_number] => 12/014119 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222473.pdf [firstpage_image] =>[orig_patent_app_number] => 12014119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9579029 [patent_doc_number] => 08769467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Method and system for utilizing hard and preferred rules for C-routing of electronic designs' [patent_app_type] => utility [patent_app_number] => 11/964639 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7742 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11964639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5548348 [patent_doc_number] => 20090158225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'METHOD AND SYSTEM FOR AUTOMATICALLY ACCESSING INTERNAL SIGNALS OR PORTS IN A DESIGN HIERARCHY' [patent_app_type] => utility [patent_app_number] => 11/955689 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158225.pdf [firstpage_image] =>[orig_patent_app_number] => 11955689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5424388 [patent_doc_number] => 20090150844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'CRITICAL PATH SELECTION FOR AT-SPEED TEST' [patent_app_type] => utility [patent_app_number] => 11/954138 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2863 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150844.pdf [firstpage_image] =>[orig_patent_app_number] => 11954138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4574193 [patent_doc_number] => 07962886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Method and system for generating design constraints' [patent_app_type] => utility [patent_app_number] => 11/952798 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7229 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962886.pdf [firstpage_image] =>[orig_patent_app_number] => 11952798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4869147 [patent_doc_number] => 20080148198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'HOTSPOT TOTALIZATION METHOD, PATTERN CORRECTION METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 11/951868 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148198.pdf [firstpage_image] =>[orig_patent_app_number] => 11951868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5577324 [patent_doc_number] => 20090144686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES' [patent_app_type] => utility [patent_app_number] => 11/948218 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6552 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144686.pdf [firstpage_image] =>[orig_patent_app_number] => 11948218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5444613 [patent_doc_number] => 20090045839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE' [patent_app_type] => utility [patent_app_number] => 11/876263 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3960 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045839.pdf [firstpage_image] =>[orig_patent_app_number] => 11876263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4774261 [patent_doc_number] => 20080059923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'LSI POWER CONSUMPTION CALCULATION METHOD AND CALCULATION PROGRAM' [patent_app_type] => utility [patent_app_number] => 11/849999 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8162 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059923.pdf [firstpage_image] =>[orig_patent_app_number] => 11849999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4470368 [patent_doc_number] => 07882452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Modeling silicon-on-insulator stress effects' [patent_app_type] => utility [patent_app_number] => 11/847999 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2431 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882452.pdf [firstpage_image] =>[orig_patent_app_number] => 11847999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4920588 [patent_doc_number] => 20080068902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Wordline Booster Design Structure and Method of Operating a Wordline Booster Circuit' [patent_app_type] => utility [patent_app_number] => 11/847759 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5178 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20080068902.pdf [firstpage_image] =>[orig_patent_app_number] => 11847759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4780901 [patent_doc_number] => 20080288900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'DETERMINATION OF SINGLE-FIX RECTIFICATION FUNCTION' [patent_app_type] => utility [patent_app_number] => 11/841079 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5557 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288900.pdf [firstpage_image] =>[orig_patent_app_number] => 11841079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5298375 [patent_doc_number] => 20090013301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Hardware definition language generation for frame-based processing' [patent_app_type] => utility [patent_app_number] => 11/842099 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11473 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013301.pdf [firstpage_image] =>[orig_patent_app_number] => 11842099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5339318 [patent_doc_number] => 20090055782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Secure Yield-aware Design Flow with Annotated Design Libraries' [patent_app_type] => utility [patent_app_number] => 11/841509 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3037 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055782.pdf [firstpage_image] =>[orig_patent_app_number] => 11841509 [rel_patent_id] =>[rel_patent_doc_number] =>)