Aric Lin

Array ( [id] => 38588 [patent_doc_number] => 07788621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and apparatus for creating layout model, computer product, and method of manufacturing device' [patent_app_type] => utility [patent_app_number] => 11/698854 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788621.pdf [firstpage_image] =>[orig_patent_app_number] => 11698854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 38588 [patent_doc_number] => 07788621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and apparatus for creating layout model, computer product, and method of manufacturing device' [patent_app_type] => utility [patent_app_number] => 11/698854 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788621.pdf [firstpage_image] =>[orig_patent_app_number] => 11698854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4449105 [patent_doc_number] => 07865857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'System and method for improved visualization and debugging of constraint circuit objects' [patent_app_type] => utility [patent_app_number] => 11/657659 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 55 [patent_no_of_words] => 21955 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865857.pdf [firstpage_image] =>[orig_patent_app_number] => 11657659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8693326 [patent_doc_number] => 08392862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-05 [patent_title] => 'Structures and methods for optimizing power consumption in an integrated chip design' [patent_app_type] => utility [patent_app_number] => 11/657228 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 6909 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11657228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4990807 [patent_doc_number] => 20070157148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Circuit layout system for automatically indicating items to wait for modification and method thereof' [patent_app_type] => utility [patent_app_number] => 11/638425 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3327 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157148.pdf [firstpage_image] =>[orig_patent_app_number] => 11638425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5255256 [patent_doc_number] => 20070136712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Semiconductor design support apparatus' [patent_app_type] => utility [patent_app_number] => 11/635661 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 11228 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20070136712.pdf [firstpage_image] =>[orig_patent_app_number] => 11635661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 27583 [patent_doc_number] => 07802214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Methods and apparatuses for timing analysis of electronics circuits' [patent_app_type] => utility [patent_app_number] => 11/635371 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4359 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802214.pdf [firstpage_image] =>[orig_patent_app_number] => 11635371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5237937 [patent_doc_number] => 20070130094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Apparatus for rapid model calculation for pattern-dependent variations in a routing system' [patent_app_type] => utility [patent_app_number] => 11/633555 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2163 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20070130094.pdf [firstpage_image] =>[orig_patent_app_number] => 11633555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837144 [patent_doc_number] => 20080134119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Automated Electrostatic Discharge Structure Placement and Routing in an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/565023 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134119.pdf [firstpage_image] =>[orig_patent_app_number] => 11565023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837141 [patent_doc_number] => 20080134116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'METHOD, COMPUTER PROGRAM PRODUCT, AND TOOL FOR TIMING PERFORMANCE OF A HIERARCHICAL CHIP DESIGN HAVING MULTIPLE PARTITION INSTANCES' [patent_app_type] => utility [patent_app_number] => 11/565192 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1398 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134116.pdf [firstpage_image] =>[orig_patent_app_number] => 11565192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837154 [patent_doc_number] => 20080134129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'DESIGN RULE CHECKING FOR ALTERNATING PHASE SHIFT LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 11/565195 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3736 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134129.pdf [firstpage_image] =>[orig_patent_app_number] => 11565195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837155 [patent_doc_number] => 20080134130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'LOCAL COLORING FOR HIERARCHICAL OPC' [patent_app_type] => utility [patent_app_number] => 11/564957 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6634 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134130.pdf [firstpage_image] =>[orig_patent_app_number] => 11564957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 284234 [patent_doc_number] => 07555737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Auxiliary method for circuit design' [patent_app_type] => utility [patent_app_number] => 11/564422 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5184 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555737.pdf [firstpage_image] =>[orig_patent_app_number] => 11564422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 313474 [patent_doc_number] => 07530043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Printed circuit board able to suppress simultaneous switching noise' [patent_app_type] => utility [patent_app_number] => 11/563158 [patent_app_country] => US [patent_app_date] => 2006-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1750 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530043.pdf [firstpage_image] =>[orig_patent_app_number] => 11563158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 235174 [patent_doc_number] => 07600203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Circuit design system and circuit design program' [patent_app_type] => utility [patent_app_number] => 11/588372 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 15103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600203.pdf [firstpage_image] =>[orig_patent_app_number] => 11588372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5231945 [patent_doc_number] => 20070294053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program' [patent_app_type] => utility [patent_app_number] => 11/586719 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20070294053.pdf [firstpage_image] =>[orig_patent_app_number] => 11586719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5122015 [patent_doc_number] => 20070143730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Design method and system for generating behavioral description model' [patent_app_type] => utility [patent_app_number] => 11/586679 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3270 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143730.pdf [firstpage_image] =>[orig_patent_app_number] => 11586679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4830506 [patent_doc_number] => 20080126999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Method and system for conducting a low-power design exploration' [patent_app_type] => utility [patent_app_number] => 11/588927 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4049 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126999.pdf [firstpage_image] =>[orig_patent_app_number] => 11588927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 171997 [patent_doc_number] => 07669165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method and system for equivalence checking of a low power design' [patent_app_type] => utility [patent_app_number] => 11/586879 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669165.pdf [firstpage_image] =>[orig_patent_app_number] => 11586879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4830532 [patent_doc_number] => 20080127020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'System and method for automatic elimination of voltage drop, also known as IR drop, violations of a mask layout block, maintaining the process design rules correctness' [patent_app_type] => utility [patent_app_number] => 11/585604 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3627 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127020.pdf [firstpage_image] =>[orig_patent_app_number] => 11585604 [rel_patent_id] =>[rel_patent_doc_number] =>)