
Aric Lin
Examiner (ID: 18708, Phone: (571)270-3090 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 605 |
| Issued Applications | 345 |
| Pending Applications | 59 |
| Abandoned Applications | 213 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5034775
[patent_doc_number] => 20070099314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'Modeling device variations in integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/586827
[patent_app_country] => US
[patent_app_date] => 2006-10-24
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[pdf_file] => publications/A1/0099/20070099314.pdf
[firstpage_image] =>[orig_patent_app_number] => 11586827
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586827 | Modeling device variations in integrated circuit design | Oct 23, 2006 | Issued |
Array
(
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[patent_doc_number] => 20070038973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout'
[patent_app_type] => utility
[patent_app_number] => 11/584737
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[firstpage_image] =>[orig_patent_app_number] => 11584737
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/584737 | Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout | Oct 18, 2006 | Issued |
Array
(
[id] => 4882105
[patent_doc_number] => 20080155488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'DEVICE FOR AVOIDING TIMING VIOLATIONS RESULTING FROM PROCESS DEFECTS IN A BACKFILLED METAL LAYER OF AN INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/538187
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[patent_app_date] => 2006-10-03
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[pdf_file] => publications/A1/0155/20080155488.pdf
[firstpage_image] =>[orig_patent_app_number] => 11538187
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538187 | Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit | Oct 2, 2006 | Issued |
Array
(
[id] => 4945623
[patent_doc_number] => 20080082950
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'Differential pair connection arrangement, and method and computer program product for making same'
[patent_app_type] => utility
[patent_app_number] => 11/540082
[patent_app_country] => US
[patent_app_date] => 2006-09-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/540082 | Differential pair connection arrangement, and method and computer program product for making same | Sep 28, 2006 | Issued |
Array
(
[id] => 4945625
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[patent_issue_date] => 2008-04-03
[patent_title] => 'Method of inclusion of sub-resolution assist feature(s)'
[patent_app_type] => utility
[patent_app_number] => 11/540214
[patent_app_country] => US
[patent_app_date] => 2006-09-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/540214 | Method of inclusion of sub-resolution assist feature(s) | Sep 28, 2006 | Abandoned |
Array
(
[id] => 5731979
[patent_doc_number] => 20060257096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Systems and methods for designing and fabricating multi-layer structures having thermal expansion properties'
[patent_app_type] => utility
[patent_app_number] => 11/441600
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[patent_app_date] => 2006-07-12
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[firstpage_image] =>[orig_patent_app_number] => 11441600
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/441600 | Systems and methods for designing and fabricating multi-layer structures having thermal expansion properties | Jul 11, 2006 | Abandoned |
Array
(
[id] => 4934936
[patent_doc_number] => 20080005711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'METHOD AND APPARATUS FOR APPROXIMATING DIAGONAL LINES IN PLACEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/424840
[patent_app_country] => US
[patent_app_date] => 2006-06-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0005/20080005711.pdf
[firstpage_image] =>[orig_patent_app_number] => 11424840
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424840 | Method and apparatus for approximating diagonal lines in placement | Jun 15, 2006 | Issued |
Array
(
[id] => 4934942
[patent_doc_number] => 20080005717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'PRIMITIVE CELL METHOD FOR FRONT END PHYSICAL DESIGN'
[patent_app_type] => utility
[patent_app_number] => 11/423240
[patent_app_country] => US
[patent_app_date] => 2006-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 11423240
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/423240 | Primitive cell method for front end physical design | Jun 8, 2006 | Issued |
Array
(
[id] => 5232538
[patent_doc_number] => 20070294647
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'Transferring software assertions to hardware design language code'
[patent_app_type] => utility
[patent_app_number] => 11/445013
[patent_app_country] => US
[patent_app_date] => 2006-06-01
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[pdf_file] => publications/A1/0294/20070294647.pdf
[firstpage_image] =>[orig_patent_app_number] => 11445013
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/445013 | Transferring software assertions to hardware design language code | May 31, 2006 | Abandoned |
Array
(
[id] => 5891070
[patent_doc_number] => 20060277021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-07
[patent_title] => 'CIRCUIT SYNTHESIS WITH SEQUENTIAL RULES'
[patent_app_type] => utility
[patent_app_number] => 11/421612
[patent_app_country] => US
[patent_app_date] => 2006-06-01
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11421612
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421612 | Circuit synthesis with sequential rules | May 31, 2006 | Issued |
Array
(
[id] => 5027285
[patent_doc_number] => 20070268731
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-22
[patent_title] => 'Layout compiler'
[patent_app_type] => utility
[patent_app_number] => 11/438777
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[firstpage_image] =>[orig_patent_app_number] => 11438777
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/438777 | Layout compiler | May 21, 2006 | Abandoned |
Array
(
[id] => 5030092
[patent_doc_number] => 20070271539
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[patent_issue_date] => 2007-11-22
[patent_title] => 'Method and apparatus for automatic creation and placement of a floor-plan region'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/438644 | Method and apparatus for automatic creation and placement of a floor-plan region | May 21, 2006 | Issued |
Array
(
[id] => 5243905
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Array
(
[id] => 5260809
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[patent_issue_date] => 2007-09-13
[patent_title] => 'A Method For Predicting Inductance And Self-Resonant Frequency Of A Spiral Inductor'
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[patent_app_number] => 11/435710
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Array
(
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Array
(
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[patent_title] => 'Method and system for debugging an electronic system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/417355 | Method and system for debugging an electronic system | May 1, 2006 | Issued |
Array
(
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[patent_title] => 'Analysis and optimization of manufacturing yield improvements'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/413133 | Compilable, reconfigurable network processor | Apr 26, 2006 | Issued |
Array
(
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[patent_title] => 'SYSTEM AND METHOD TO POWER ROUTE HIERARCHICAL DESIGNS THAT EMPLOY MACRO REUSE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/380236 | SYSTEM AND METHOD TO POWER ROUTE HIERARCHICAL DESIGNS THAT EMPLOY MACRO REUSE | Apr 25, 2006 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/408740 | Synthesis of fast squarer functional blocks | Apr 20, 2006 | Issued |