Aric Lin

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Array ( [id] => 18651912 [patent_doc_number] => 20230297748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => HIERARCHICAL FLOOR-PLANNING FOR RAPID FPGA PROTOTYPING [patent_app_type] => utility [patent_app_number] => 17/695093 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695093 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 18454705 [patent_doc_number] => 20230195985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => FLEXIBLE MODELING METHOD FOR TIMING CONSTRAINT OF REGISTER [patent_app_type] => utility [patent_app_number] => 18/014002 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18014002 [rel_patent_id] =>[rel_patent_doc_number] =>)

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