Aric Lin

Array ( [id] => 223673 [patent_doc_number] => 07610570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-27 [patent_title] => 'Method and mechanism for using systematic local search for SAT solving' [patent_app_type] => utility [patent_app_number] => 11/407864 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4449 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610570.pdf [firstpage_image] =>[orig_patent_app_number] => 11407864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5058847 [patent_doc_number] => 20070061769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Layout method and layout program for semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/401310 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5520 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061769.pdf [firstpage_image] =>[orig_patent_app_number] => 11401310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8247240 [patent_doc_number] => 08205186 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-19 [patent_title] => 'Incremental modification of instrumentation logic' [patent_app_type] => utility [patent_app_number] => 11/400590 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/205/08205186.pdf [firstpage_image] =>[orig_patent_app_number] => 11400590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 860587 [patent_doc_number] => 07376920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method to monitor critical dimension of IC interconnect' [patent_app_type] => utility [patent_app_number] => 11/398980 [patent_app_country] => US [patent_app_date] => 2006-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5512 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376920.pdf [firstpage_image] =>[orig_patent_app_number] => 11398980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 832763 [patent_doc_number] => 07401310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-15 [patent_title] => 'Integrated circuit design with cell-based macros' [patent_app_type] => utility [patent_app_number] => 11/397550 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/401/07401310.pdf [firstpage_image] =>[orig_patent_app_number] => 11397550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7589208 [patent_doc_number] => 07665056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-16 [patent_title] => 'Method and system for dynamic placement of bond fingers on integrated circuit package' [patent_app_type] => utility [patent_app_number] => 11/354826 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6079 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665056.pdf [firstpage_image] =>[orig_patent_app_number] => 11354826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5928351 [patent_doc_number] => 20060242618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Lithographic simulations using graphical processing units' [patent_app_type] => utility [patent_app_number] => 11/354398 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3748 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242618.pdf [firstpage_image] =>[orig_patent_app_number] => 11354398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5891620 [patent_doc_number] => 20060277234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'A compact processor element for a scalable digital logic verification and emulation system' [patent_app_type] => utility [patent_app_number] => 11/307130 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277234.pdf [firstpage_image] =>[orig_patent_app_number] => 11307130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5217524 [patent_doc_number] => 20070158835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Method for designing interconnect for a new processing technology' [patent_app_type] => utility [patent_app_number] => 11/332566 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2475 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158835.pdf [firstpage_image] =>[orig_patent_app_number] => 11332566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5657252 [patent_doc_number] => 20060142988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Design methodology and manufacturing method for semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/318431 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10436 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20060142988.pdf [firstpage_image] =>[orig_patent_app_number] => 11318431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 87959 [patent_doc_number] => 07743356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Method of disposing dummy pattern' [patent_app_type] => utility [patent_app_number] => 11/306392 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9491 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743356.pdf [firstpage_image] =>[orig_patent_app_number] => 11306392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5081485 [patent_doc_number] => 20070124709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Method and system for design rule checking for an SiP device' [patent_app_type] => utility [patent_app_number] => 11/287767 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7041 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20070124709.pdf [firstpage_image] =>[orig_patent_app_number] => 11287767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5042348 [patent_doc_number] => 20070094630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Power grid design in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/163520 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7682 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094630.pdf [firstpage_image] =>[orig_patent_app_number] => 11163520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 823621 [patent_doc_number] => 07409657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Clock tree layout method for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/243189 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2852 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409657.pdf [firstpage_image] =>[orig_patent_app_number] => 11243189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5816690 [patent_doc_number] => 20060085781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Library for computer-based tool and related system and method' [patent_app_type] => utility [patent_app_number] => 11/243506 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20952 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20060085781.pdf [firstpage_image] =>[orig_patent_app_number] => 11243506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5684520 [patent_doc_number] => 20060200790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Model-based SRAF insertion' [patent_app_type] => utility [patent_app_number] => 11/241732 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3870 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200790.pdf [firstpage_image] =>[orig_patent_app_number] => 11241732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 235222 [patent_doc_number] => 07600210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-06 [patent_title] => 'Method and apparatus for modular circuit design for a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/238433 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5722 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600210.pdf [firstpage_image] =>[orig_patent_app_number] => 11238433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 294272 [patent_doc_number] => 07546572 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-09 [patent_title] => 'Shared memory interface in a programmable logic device using partial reconfiguration' [patent_app_type] => utility [patent_app_number] => 11/230879 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7359 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546572.pdf [firstpage_image] =>[orig_patent_app_number] => 11230879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 86924 [patent_doc_number] => 07747977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-29 [patent_title] => 'Method and system for stencil design for particle beam writing' [patent_app_type] => utility [patent_app_number] => 11/226253 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7593 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/747/07747977.pdf [firstpage_image] =>[orig_patent_app_number] => 11226253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 146889 [patent_doc_number] => 07689966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Methods, systems, and carrier media for evaluating reticle layout data' [patent_app_type] => utility [patent_app_number] => 11/226698 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12829 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689966.pdf [firstpage_image] =>[orig_patent_app_number] => 11226698 [rel_patent_id] =>[rel_patent_doc_number] =>)