Search

Aric Lin

Examiner (ID: 18708, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
605
Issued Applications
345
Pending Applications
59
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5615357 [patent_doc_number] => 20060117287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Method and device for checking a circuit for adherence to set-up and hold times' [patent_app_type] => utility [patent_app_number] => 11/226514 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5817 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117287.pdf [firstpage_image] =>[orig_patent_app_number] => 11226514 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226514
Method and device for checking a circuit for adherence to set-up and hold times Sep 12, 2005 Issued
Array ( [id] => 5058844 [patent_doc_number] => 20070061766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method and system for performing target enlargement in the presence of constraints' [patent_app_type] => utility [patent_app_number] => 11/225672 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061766.pdf [firstpage_image] =>[orig_patent_app_number] => 11225672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225672
Method and system for performing target enlargement in the presence of constraints Sep 12, 2005 Issued
Array ( [id] => 336988 [patent_doc_number] => 07509617 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements' [patent_app_type] => utility [patent_app_number] => 11/225248 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509617.pdf [firstpage_image] =>[orig_patent_app_number] => 11225248 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225248
Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements Sep 11, 2005 Issued
Array ( [id] => 5621326 [patent_doc_number] => 20060190861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method and apparatus for evaluating coverage of circuit, and computer product' [patent_app_type] => utility [patent_app_number] => 11/214843 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5557 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190861.pdf [firstpage_image] =>[orig_patent_app_number] => 11214843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214843
Method and apparatus for evaluating coverage of circuit, and computer product Aug 30, 2005 Abandoned
Array ( [id] => 313463 [patent_doc_number] => 07530035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Automatic power grid synthesis method and computer readable recording medium for storing program thereof' [patent_app_type] => utility [patent_app_number] => 11/212295 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3567 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530035.pdf [firstpage_image] =>[orig_patent_app_number] => 11212295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212295
Automatic power grid synthesis method and computer readable recording medium for storing program thereof Aug 24, 2005 Issued
Array ( [id] => 8001367 [patent_doc_number] => 08082531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Method and an apparatus to design a processing system using a graphical user interface' [patent_app_type] => utility [patent_app_number] => 11/201627 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082531.pdf [firstpage_image] =>[orig_patent_app_number] => 11201627 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201627
Method and an apparatus to design a processing system using a graphical user interface Aug 9, 2005 Issued
Array ( [id] => 4923881 [patent_doc_number] => 20080072198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations' [patent_app_type] => utility [patent_app_number] => 11/629445 [patent_app_country] => US [patent_app_date] => 2005-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7611 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072198.pdf [firstpage_image] =>[orig_patent_app_number] => 11629445 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/629445
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations Jun 10, 2005 Issued
Array ( [id] => 355786 [patent_doc_number] => 07493583 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Method and apparatus for controlling crosstalk, power and yield in nanometer technology ICs' [patent_app_type] => utility [patent_app_number] => 11/150866 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3840 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493583.pdf [firstpage_image] =>[orig_patent_app_number] => 11150866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/150866
Method and apparatus for controlling crosstalk, power and yield in nanometer technology ICs Jun 9, 2005 Issued
Array ( [id] => 8971873 [patent_doc_number] => 08510703 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-13 [patent_title] => 'Method and mechanism for implementing PCB routing' [patent_app_type] => utility [patent_app_number] => 11/098039 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4648 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11098039 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098039
Method and mechanism for implementing PCB routing Mar 31, 2005 Issued
Array ( [id] => 128321 [patent_doc_number] => 07707537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Method and apparatus for generating layout regions with local preferred directions' [patent_app_type] => utility [patent_app_number] => 11/005162 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 10189 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707537.pdf [firstpage_image] =>[orig_patent_app_number] => 11005162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005162
Method and apparatus for generating layout regions with local preferred directions Dec 5, 2004 Issued
Array ( [id] => 5867178 [patent_doc_number] => 20060101309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Debugging simulation of a circuit core using pattern recorder, player & checker' [patent_app_type] => utility [patent_app_number] => 10/971911 [patent_app_country] => US [patent_app_date] => 2004-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7252 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101309.pdf [firstpage_image] =>[orig_patent_app_number] => 10971911 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971911
Debugging simulation of a circuit core using pattern recorder, player and checker Oct 22, 2004 Issued
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