
Aric Lin
Examiner (ID: 18708, Phone: (571)270-3090 , Office: P/2851 )
| Most Active Art Unit | |
| Art Unit(s) | |
| Total Applications | |
| Issued Applications | |
| Pending Applications | |
| Abandoned Applications |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 11/226514 | Method and device for checking a circuit for adherence to set-up and hold times | Sep 12, 2005 | Issued |
| 11/225672 | Method and system for performing target enlargement in the presence of constraints | Sep 12, 2005 | Issued |
| 11/225248 | Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements | Sep 11, 2005 | Issued |
| 11/214843 | Method and apparatus for evaluating coverage of circuit, and computer product | Aug 30, 2005 | Abandoned |
| 11/212295 | Automatic power grid synthesis method and computer readable recording medium for storing program thereof | Aug 24, 2005 | Issued |
| 11/201627 | Method and an apparatus to design a processing system using a graphical user interface | Aug 9, 2005 | Issued |
| 11/629445 | Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations | Jun 10, 2005 | Issued |
| 11/150866 | Method and apparatus for controlling crosstalk, power and yield in nanometer technology ICs | Jun 9, 2005 | Issued |
| 11/098039 | Method and mechanism for implementing PCB routing | Mar 31, 2005 | Issued |
| 11/005162 | Method and apparatus for generating layout regions with local preferred directions | Dec 5, 2004 | Issued |
| 10/971911 | Debugging simulation of a circuit core using pattern recorder, player and checker | Oct 22, 2004 | Issued |