Search

Aric Lin

Examiner (ID: 18708, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
605
Issued Applications
345
Pending Applications
59
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18954554 [patent_doc_number] => 20240042881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SYSTEMS AND METHODS FOR PRE-CHARGING VEHICLE-TO-LOAD CHARGER [patent_app_type] => utility [patent_app_number] => 17/761022 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17761022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/761022
SYSTEMS AND METHODS FOR PRE-CHARGING VEHICLE-TO-LOAD CHARGER Sep 19, 2021 Pending
Array ( [id] => 18240424 [patent_doc_number] => 20230072735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => REFINEMENT OF AN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/468340 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468340
REFINEMENT OF AN INTEGRATED CIRCUIT DESIGN Sep 6, 2021 Pending
Array ( [id] => 19719293 [patent_doc_number] => 12204832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Logical clock connection in an integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/468319 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 40 [patent_no_of_words] => 27045 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468319
Logical clock connection in an integrated circuit design Sep 6, 2021 Issued
Array ( [id] => 18242217 [patent_doc_number] => 20230074528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => ITERATIVE DESIGN OF AN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/468278 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468278
ITERATIVE DESIGN OF AN INTEGRATED CIRCUIT DESIGN Sep 6, 2021 Pending
Array ( [id] => 19340660 [patent_doc_number] => 12050852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Signal pre-routing in an integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/468243 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 40 [patent_no_of_words] => 26656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468243 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468243
Signal pre-routing in an integrated circuit design Sep 6, 2021 Issued
Array ( [id] => 17462615 [patent_doc_number] => 20220075920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => Automated Debug of Falsified Power-Aware Formal Properties using Static Checker Results [patent_app_type] => utility [patent_app_number] => 17/463040 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463040
Automated Debug of Falsified Power-Aware Formal Properties using Static Checker Results Aug 30, 2021 Abandoned
Array ( [id] => 18401253 [patent_doc_number] => 11663391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Latch-up avoidance for sea-of-gates [patent_app_type] => utility [patent_app_number] => 17/411113 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7678 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411113
Latch-up avoidance for sea-of-gates Aug 24, 2021 Issued
Array ( [id] => 18155133 [patent_doc_number] => 11568113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Variation-aware delay fault testing [patent_app_type] => utility [patent_app_number] => 17/411346 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411346 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411346
Variation-aware delay fault testing Aug 24, 2021 Issued
Array ( [id] => 19212705 [patent_doc_number] => 12001768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-04 [patent_title] => Enhanced glitch estimation in vectorless power analysis [patent_app_type] => utility [patent_app_number] => 17/411578 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7066 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411578
Enhanced glitch estimation in vectorless power analysis Aug 24, 2021 Issued
Array ( [id] => 17432319 [patent_doc_number] => 20220060029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Battery Control Device and Battery System [patent_app_type] => utility [patent_app_number] => 17/406190 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406190
Battery control device and battery system Aug 18, 2021 Issued
Array ( [id] => 19842940 [patent_doc_number] => 12255344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Battery pack and combination of the battery pack and a power tool [patent_app_type] => utility [patent_app_number] => 17/406179 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4630 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406179
Battery pack and combination of the battery pack and a power tool Aug 18, 2021 Issued
Array ( [id] => 17868558 [patent_doc_number] => 20220291294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => INSULATION RESISTANCE DETECTION SYSTEM FOR ELECTRIC VEHICLE AND INSULATION RESISTANCE DETECTION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/406644 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406644
Insulation resistance detection system for electric vehicle and insulation resistance detection method thereof Aug 18, 2021 Issued
Array ( [id] => 17432320 [patent_doc_number] => 20220060030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Power Feeding Control Device, Power Feeding System, and Power Feeding Method [patent_app_type] => utility [patent_app_number] => 17/406329 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406329
Power feeding control device, power feeding system, and power feeding method Aug 18, 2021 Issued
Array ( [id] => 18212864 [patent_doc_number] => 20230059128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => DCDC Converter [patent_app_type] => utility [patent_app_number] => 17/445493 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445493
DCDC Converter Aug 18, 2021 Abandoned
Array ( [id] => 18370949 [patent_doc_number] => 11651127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Placement of logic based on relative activation rates [patent_app_type] => utility [patent_app_number] => 17/399523 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399523
Placement of logic based on relative activation rates Aug 10, 2021 Issued
Array ( [id] => 17261332 [patent_doc_number] => 20210374317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERSION AND SYSTEM OF GENERATING SAME [patent_app_type] => utility [patent_app_number] => 17/396523 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396523
METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERSION AND SYSTEM OF GENERATING SAME Aug 5, 2021 Pending
Array ( [id] => 17416043 [patent_doc_number] => 20220050947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => GLOBAL MISTRACKING ANALYSIS IN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/395277 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395277
Global mistracking analysis in integrated circuit design Aug 4, 2021 Issued
Array ( [id] => 18168783 [patent_doc_number] => 20230035394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => ELECTRONIC CIRCUITS INCLUDING HYBRID VOLTAGE THRESHOLD LOGICAL ENTITIES [patent_app_type] => utility [patent_app_number] => 17/388121 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388121
Electronic circuits including hybrid voltage threshold logical entities Jul 28, 2021 Issued
Array ( [id] => 17401864 [patent_doc_number] => 20220043954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METHODS AND SYSTEMS FOR VERIFYING A PROPERTY OF AN INTEGRATED CIRCUIT HARDWARE DESIGN USING A QUIESCENT STATE [patent_app_type] => utility [patent_app_number] => 17/382674 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382674
Methods and systems for verifying a property of an integrated circuit hardware design using a quiescent state Jul 21, 2021 Issued
Array ( [id] => 17371765 [patent_doc_number] => 20220026817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => DETERMINING SUBSTRATE PROFILE PROPERTIES USING MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/379707 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379707
DETERMINING SUBSTRATE PROFILE PROPERTIES USING MACHINE LEARNING Jul 18, 2021 Pending
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