Search

Aric Lin

Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
60
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18212864 [patent_doc_number] => 20230059128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => DCDC Converter [patent_app_type] => utility [patent_app_number] => 17/445493 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445493
DCDC Converter Aug 18, 2021 Abandoned
Array ( [id] => 18370949 [patent_doc_number] => 11651127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Placement of logic based on relative activation rates [patent_app_type] => utility [patent_app_number] => 17/399523 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399523
Placement of logic based on relative activation rates Aug 10, 2021 Issued
Array ( [id] => 17261332 [patent_doc_number] => 20210374317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERSION AND SYSTEM OF GENERATING SAME [patent_app_type] => utility [patent_app_number] => 17/396523 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396523
METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERSION AND SYSTEM OF GENERATING SAME Aug 5, 2021 Pending
Array ( [id] => 17416043 [patent_doc_number] => 20220050947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => GLOBAL MISTRACKING ANALYSIS IN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/395277 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395277
Global mistracking analysis in integrated circuit design Aug 4, 2021 Issued
Array ( [id] => 18168783 [patent_doc_number] => 20230035394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => ELECTRONIC CIRCUITS INCLUDING HYBRID VOLTAGE THRESHOLD LOGICAL ENTITIES [patent_app_type] => utility [patent_app_number] => 17/388121 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388121
Electronic circuits including hybrid voltage threshold logical entities Jul 28, 2021 Issued
Array ( [id] => 17401864 [patent_doc_number] => 20220043954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METHODS AND SYSTEMS FOR VERIFYING A PROPERTY OF AN INTEGRATED CIRCUIT HARDWARE DESIGN USING A QUIESCENT STATE [patent_app_type] => utility [patent_app_number] => 17/382674 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382674
Methods and systems for verifying a property of an integrated circuit hardware design using a quiescent state Jul 21, 2021 Issued
Array ( [id] => 17371765 [patent_doc_number] => 20220026817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => DETERMINING SUBSTRATE PROFILE PROPERTIES USING MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/379707 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379707
DETERMINING SUBSTRATE PROFILE PROPERTIES USING MACHINE LEARNING Jul 18, 2021 Pending
Array ( [id] => 17358924 [patent_doc_number] => 20220019720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => FRAMEWORK FOR AUTOMATED SYNTHESIS OF SECURE, OPTIMIZED SYSTEM-ON-CHIP ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 17/375790 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375790
FRAMEWORK FOR AUTOMATED SYNTHESIS OF SECURE, OPTIMIZED SYSTEM-ON-CHIP ARCHITECTURES Jul 13, 2021 Abandoned
Array ( [id] => 17346063 [patent_doc_number] => 20220012394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => ELECTRONIC SIGNAL VERIFICATION USING A TRANSLATED SIMULATED WAVEFORM [patent_app_type] => utility [patent_app_number] => 17/370930 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370930
ELECTRONIC SIGNAL VERIFICATION USING A TRANSLATED SIMULATED WAVEFORM Jul 7, 2021 Abandoned
Array ( [id] => 17629495 [patent_doc_number] => 20220164510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => AUTOMATED DESIGN OF FIELD PROGRAMMABLE GATE ARRAY OR OTHER LOGIC DEVICE BASED ON ARTIFICIAL INTELLIGENCE AND VECTORIZATION OF BEHAVIORAL SOURCE CODE [patent_app_type] => utility [patent_app_number] => 17/364565 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364565
AUTOMATED DESIGN OF FIELD PROGRAMMABLE GATE ARRAY OR OTHER LOGIC DEVICE BASED ON ARTIFICIAL INTELLIGENCE AND VECTORIZATION OF BEHAVIORAL SOURCE CODE Jun 29, 2021 Abandoned
Array ( [id] => 18668819 [patent_doc_number] => 11775723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-03 [patent_title] => Methods, systems, and computer program products for efficiently implementing a 3D-IC [patent_app_type] => utility [patent_app_number] => 17/364388 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364388
Methods, systems, and computer program products for efficiently implementing a 3D-IC Jun 29, 2021 Issued
Array ( [id] => 17598104 [patent_doc_number] => 20220147678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SYSTEMS AND METHODS FOR CAPACITANCE EXTRACTION [patent_app_type] => utility [patent_app_number] => 17/363298 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363298
SYSTEMS AND METHODS FOR CAPACITANCE EXTRACTION Jun 29, 2021 Pending
Array ( [id] => 18430730 [patent_doc_number] => 11675952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Integrated circuit, system and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/345361 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 56 [patent_no_of_words] => 37094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345361
Integrated circuit, system and method of forming the same Jun 10, 2021 Issued
Array ( [id] => 17970389 [patent_doc_number] => 11487924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information [patent_app_type] => utility [patent_app_number] => 17/346194 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346194
System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information Jun 10, 2021 Issued
Array ( [id] => 17261329 [patent_doc_number] => 20210374314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Engineering Change Order Scenario Compression by Applying Hybrid of Live and Static Timing Views [patent_app_type] => utility [patent_app_number] => 17/332861 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332861
Engineering Change Order Scenario Compression by Applying Hybrid of Live and Static Timing Views May 26, 2021 Pending
Array ( [id] => 17216364 [patent_doc_number] => 20210349702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION [patent_app_type] => utility [patent_app_number] => 17/328878 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328878 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328878
CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION May 23, 2021 Abandoned
Array ( [id] => 20820154 [patent_doc_number] => 12675625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-07 [patent_title] => Protecting against emission based side channel detection [patent_app_type] => utility [patent_app_number] => 17/319286 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9285 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319286 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319286
Protecting against emission based side channel detection May 12, 2021 Issued
Array ( [id] => 17054660 [patent_doc_number] => 20210264094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/319687 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319687 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319687
Integrated circuit stack verification method and system for performing the same May 12, 2021 Issued
Array ( [id] => 19828063 [patent_doc_number] => 12248847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Communication coordination and node synchronization for enhanced quantum circuit operation employing a hybrid classical/quantum system [patent_app_type] => utility [patent_app_number] => 17/307270 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 42026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307270 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/307270
Communication coordination and node synchronization for enhanced quantum circuit operation employing a hybrid classical/quantum system May 3, 2021 Issued
Array ( [id] => 17024433 [patent_doc_number] => 20210248305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => SYSTEM AND METHOD FOR INTERACTIVE DATASHEETS [patent_app_type] => utility [patent_app_number] => 17/243199 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243199
SYSTEM AND METHOD FOR INTERACTIVE DATASHEETS Apr 27, 2021 Pending
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