Search

Aric Lin

Examiner (ID: 18708, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
605
Issued Applications
345
Pending Applications
59
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18889922 [patent_doc_number] => 11868695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Driver resizing using a transition-based pin capacitance increase margin [patent_app_type] => utility [patent_app_number] => 17/219730 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6380 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219730
Driver resizing using a transition-based pin capacitance increase margin Mar 30, 2021 Issued
Array ( [id] => 17915161 [patent_doc_number] => 20220317557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => OPTICAL PROXIMITY CORRECTION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/310883 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310883 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/310883
OPTICAL PROXIMITY CORRECTION METHOD AND APPARATUS Mar 28, 2021 Abandoned
Array ( [id] => 17899709 [patent_doc_number] => 20220309371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => AUTOMATED QUANTUM CIRCUIT JOB SUBMISSION AND STATUS DETERMINATION [patent_app_type] => utility [patent_app_number] => 17/216505 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216505
AUTOMATED QUANTUM CIRCUIT JOB SUBMISSION AND STATUS DETERMINATION Mar 28, 2021 Pending
Array ( [id] => 18446272 [patent_doc_number] => 11681844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-20 [patent_title] => Configurable testing of semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/216508 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216508
Configurable testing of semiconductor devices Mar 28, 2021 Issued
Array ( [id] => 16947588 [patent_doc_number] => 20210206279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => CHARGING SCOOTERS WITHIN ELECTRIC SCOOTER DOCKING STATIONS [patent_app_type] => utility [patent_app_number] => 17/211665 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211665
CHARGING SCOOTERS WITHIN ELECTRIC SCOOTER DOCKING STATIONS Mar 23, 2021 Pending
Array ( [id] => 17084385 [patent_doc_number] => 20210279392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => GLITCH POWER ANALYSIS WITH REGISTER TRANSISTOR LEVEL VECTORS [patent_app_type] => utility [patent_app_number] => 17/192420 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192420
Glitch power analysis with register transfer level vectors Mar 3, 2021 Issued
Array ( [id] => 17907665 [patent_doc_number] => 11461520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-04 [patent_title] => SDD ATPG using fault rules files, SDF and node slack for testing an IC chip [patent_app_type] => utility [patent_app_number] => 17/180239 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 19954 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180239
SDD ATPG using fault rules files, SDF and node slack for testing an IC chip Feb 18, 2021 Issued
Array ( [id] => 17809688 [patent_doc_number] => 20220261523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => BEHAVIORAL-LEVEL TIMING AND AREA OPTIMIATION [patent_app_type] => utility [patent_app_number] => 17/177778 [patent_app_country] => US [patent_app_date] => 2021-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17177778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/177778
BEHAVIORAL-LEVEL TIMING AND AREA OPTIMIATION Feb 16, 2021 Abandoned
Array ( [id] => 16872682 [patent_doc_number] => 20210166149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => QUANTUM NOISE PROCESS ANALYSIS METHOD AND APPARATUS, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/174665 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174665
Quantum noise process analysis method and apparatus, device, and storage medium Feb 11, 2021 Issued
Array ( [id] => 17009736 [patent_doc_number] => 20210240897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SYSTEM AND METHOD FOR CAPTURING HARDWARE EMULATION DATA [patent_app_type] => utility [patent_app_number] => 17/163157 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163157
SYSTEM AND METHOD FOR CAPTURING HARDWARE EMULATION DATA Jan 28, 2021 Pending
Array ( [id] => 16981532 [patent_doc_number] => 20210225769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => INTEGRATED CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/152802 [patent_app_country] => US [patent_app_date] => 2021-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152802
INTEGRATED CIRCUIT STRUCTURE Jan 19, 2021 Abandoned
Array ( [id] => 17736952 [patent_doc_number] => 20220222411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => METHOD AND SYSTEM FOR DESIGNING AN INTEGRATED CIRCUIT, AND AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/147854 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147854
Method and system for designing an integrated circuit, and an integrated circuit Jan 12, 2021 Issued
Array ( [id] => 18446274 [patent_doc_number] => 11681846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-20 [patent_title] => Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs [patent_app_type] => utility [patent_app_number] => 17/147163 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6990 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147163
Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs Jan 11, 2021 Issued
Array ( [id] => 16887797 [patent_doc_number] => 20210173994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => METHOD AND SYSTEM FOR VIEWING SIMULATION SIGNALS OF A DIGITAL PRODUCT [patent_app_type] => utility [patent_app_number] => 17/139323 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139323
METHOD AND SYSTEM FOR VIEWING SIMULATION SIGNALS OF A DIGITAL PRODUCT Dec 30, 2020 Abandoned
Array ( [id] => 18047002 [patent_doc_number] => 11520958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Verifying a hardware design for a multi-stage component [patent_app_type] => utility [patent_app_number] => 17/135146 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 22273 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135146 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135146
Verifying a hardware design for a multi-stage component Dec 27, 2020 Issued
Array ( [id] => 16750993 [patent_doc_number] => 20210103002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => Method and Apparatus for Estimating State of Charge of Battery [patent_app_type] => utility [patent_app_number] => 17/126895 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126895
Method and Apparatus for Estimating State of Charge of Battery Dec 17, 2020 Abandoned
Array ( [id] => 16905570 [patent_doc_number] => 20210184486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => PRE-CHARGING CIRCUIT AND PRE-CHARGING METHOD [patent_app_type] => utility [patent_app_number] => 17/123022 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123022
PRE-CHARGING CIRCUIT AND PRE-CHARGING METHOD Dec 14, 2020 Pending
Array ( [id] => 20417154 [patent_doc_number] => 12500449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Wireless charging apparatus and terminal using same [patent_app_type] => utility [patent_app_number] => 17/113328 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113328
Wireless charging apparatus and terminal using same Dec 6, 2020 Issued
Array ( [id] => 16780527 [patent_doc_number] => 20210117606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => INTEGRATED CIRCUIT LAYOUT DIAGRAM SYSTEM [patent_app_type] => utility [patent_app_number] => 17/111014 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111014
INTEGRATED CIRCUIT LAYOUT DIAGRAM SYSTEM Dec 2, 2020 Pending
Array ( [id] => 18331000 [patent_doc_number] => 11636246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Systems and methods for predicting and managing power and energy use of semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/100016 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 11562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100016
Systems and methods for predicting and managing power and energy use of semiconductor devices Nov 19, 2020 Issued
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