Aric Lin

Array ( [id] => 17847021 [patent_doc_number] => 11436398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Simulating large cat qubits using a shifted fock basis [patent_app_type] => utility [patent_app_number] => 17/098245 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 45 [patent_no_of_words] => 27749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16809593 [patent_doc_number] => 20210132147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => TEST PATTERN GENERATING METHOD, TEST PATTERN GENERATING DEVICE AND FAULT MODEL GENERATING METHOD [patent_app_type] => utility [patent_app_number] => 17/073427 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17715651 [patent_doc_number] => 11379644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-05 [patent_title] => IC chip test engine [patent_app_type] => utility [patent_app_number] => 17/064406 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16950590 [patent_doc_number] => 20210209282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => METHOD FOR COMPENSATING VOLTAGE DROP WITH ADDITIONAL POWER MESH AND CIRCUIT SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 17/037870 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16964509 [patent_doc_number] => 20210216008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => CORRECTION METHOD OF MASK LAYOUT AND MASK CONTAINING CORRECTED LAYOUT [patent_app_type] => utility [patent_app_number] => 17/037613 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17507835 [patent_doc_number] => 20220100938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Flexible Cell Height Layout Architecture [patent_app_type] => utility [patent_app_number] => 17/035951 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18159926 [patent_doc_number] => 20230026518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => IMPURITY-CENTER-BASED QUANTUM COMPUTER [patent_app_type] => utility [patent_app_number] => 17/772228 [patent_app_country] => US [patent_app_date] => 2020-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 155961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17772228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17986691 [patent_doc_number] => 20220352728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => VARIABLE STEP SIZE EQUALIZATION PROCESSING METHOD, AND DEVICE, MEDIUM, BATTERY PACKAGE, AND VEHICLE [patent_app_type] => utility [patent_app_number] => 17/763943 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17763943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18130474 [patent_doc_number] => 11556685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-17 [patent_title] => Time-based power analysis [patent_app_type] => utility [patent_app_number] => 16/948280 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6977 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16693979 [patent_doc_number] => 20210076458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => FLAT COIL CARRIER [patent_app_type] => utility [patent_app_number] => 17/013521 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17430616 [patent_doc_number] => 20220058325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Method for Recognizing Analog Circuit Structure [patent_app_type] => utility [patent_app_number] => 16/996540 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18174107 [patent_doc_number] => 11573817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Compiler-driver programmable device virtualization in a computing system [patent_app_type] => utility [patent_app_number] => 16/934332 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17763742 [patent_doc_number] => 20220237354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => GENERATING DIGITAL CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/627332 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17627332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16616152 [patent_doc_number] => 20210034805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => METHOD AND APPARATUS FOR AUTOMATIC EXTRACTION OF STANDARD CELLS TO GENERATE A STANDARD CELL CANDIDATE LIBRARY [patent_app_type] => utility [patent_app_number] => 16/927195 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19653384 [patent_doc_number] => 12175175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Systems and methods for generating synthesizable netlists from register transfer level designs [patent_app_type] => utility [patent_app_number] => 16/925500 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17151620 [patent_doc_number] => 11144698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Method, system, and product for an improved approach to placement and optimization in a physical design flow [patent_app_type] => utility [patent_app_number] => 16/946677 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16946677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18415230 [patent_doc_number] => 11669773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same [patent_app_type] => utility [patent_app_number] => 16/915786 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16714443 [patent_doc_number] => 20210081590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SYSTEM LEVEL SIMULATION AND EVALUATION OF CAPACITIVE AND INDUCTIVE SENSING-BASED SOLUTIONS [patent_app_type] => utility [patent_app_number] => 16/903217 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16828507 [patent_doc_number] => 20210143800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => HYBRID STANDARD CELL AND METHOD OF DESIGNING INTEGRATED CIRCUIT USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/891521 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16543738 [patent_doc_number] => 20200410153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => AUTOMATED CIRCUIT GENERATION [patent_app_type] => utility [patent_app_number] => 16/882217 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 64577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882217 [rel_patent_id] =>[rel_patent_doc_number] =>)