
Aric Lin
Examiner (ID: 18708, Phone: (571)270-3090 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 605 |
| Issued Applications | 345 |
| Pending Applications | 59 |
| Abandoned Applications | 213 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16927355
[patent_doc_number] => 11048841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-29
[patent_title] => System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information
[patent_app_type] => utility
[patent_app_number] => 16/875181
[patent_app_country] => US
[patent_app_date] => 2020-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6907
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875181
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/875181 | System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information | May 14, 2020 | Issued |
Array
(
[id] => 17824822
[patent_doc_number] => 11429770
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-30
[patent_title] => System, method, and computer program product for analyzing X-propagation simulations
[patent_app_type] => utility
[patent_app_number] => 16/869820
[patent_app_country] => US
[patent_app_date] => 2020-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6147
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869820
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/869820 | System, method, and computer program product for analyzing X-propagation simulations | May 7, 2020 | Issued |
Array
(
[id] => 18303618
[patent_doc_number] => 11625522
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-11
[patent_title] => Method and apparatus for generating three-dimensional integrated circuit design
[patent_app_type] => utility
[patent_app_number] => 16/861286
[patent_app_country] => US
[patent_app_date] => 2020-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 7575
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 389
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861286
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/861286 | Method and apparatus for generating three-dimensional integrated circuit design | Apr 28, 2020 | Issued |
Array
(
[id] => 16240612
[patent_doc_number] => 20200257846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE
[patent_app_type] => utility
[patent_app_number] => 16/859325
[patent_app_country] => US
[patent_app_date] => 2020-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5089
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859325
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/859325 | Checking wafer-level integrated designs for rule compliance | Apr 26, 2020 | Issued |
Array
(
[id] => 17598101
[patent_doc_number] => 20220147675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => METHOD OF REALIZING A HARDWARE DEVICE FOR EXECUTING OPERATIONS DEFINED BY A HIGH-LEVEL SOFTWARE CODE
[patent_app_type] => utility
[patent_app_number] => 17/594586
[patent_app_country] => US
[patent_app_date] => 2020-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8405
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 325
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17594586
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/594586 | Method of realizing a hardware device for executing operations defined by a high-level software code | Apr 22, 2020 | Issued |
Array
(
[id] => 16226815
[patent_doc_number] => 20200251932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-06
[patent_title] => LOW-HEAT WIRELESS POWER RECEIVING DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/856654
[patent_app_country] => US
[patent_app_date] => 2020-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5075
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856654
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/856654 | LOW-HEAT WIRELESS POWER RECEIVING DEVICE AND METHOD | Apr 22, 2020 | Pending |
Array
(
[id] => 16424114
[patent_doc_number] => 20200349312
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-05
[patent_title] => Core-Only System Management Interrupt
[patent_app_type] => utility
[patent_app_number] => 16/854788
[patent_app_country] => US
[patent_app_date] => 2020-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19669
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854788
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/854788 | Core-Only System Management Interrupt | Apr 20, 2020 | Abandoned |
Array
(
[id] => 17131049
[patent_doc_number] => 20210305818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => High Efficiency Bidirectional Charge Balancing of Battery Cells
[patent_app_type] => utility
[patent_app_number] => 16/831583
[patent_app_country] => US
[patent_app_date] => 2020-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831583
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/831583 | High Efficiency Bidirectional Charge Balancing of Battery Cells | Mar 25, 2020 | Abandoned |
Array
(
[id] => 16300068
[patent_doc_number] => 20200285791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-10
[patent_title] => CIRCUIT DESIGN METHOD AND ASSOCIATED COMPUTER PROGRAM PRODUCT
[patent_app_type] => utility
[patent_app_number] => 16/802573
[patent_app_country] => US
[patent_app_date] => 2020-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1572
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802573
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/802573 | CIRCUIT DESIGN METHOD AND ASSOCIATED COMPUTER PROGRAM PRODUCT | Feb 26, 2020 | Abandoned |
Array
(
[id] => 16240753
[patent_doc_number] => 20200257987
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => SYSTEMS AND METHODS FOR HYBRID QUANTUM-CLASSICAL COMPUTING
[patent_app_type] => utility
[patent_app_number] => 16/785125
[patent_app_country] => US
[patent_app_date] => 2020-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5921
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785125
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/785125 | Systems and methods for hybrid quantum-classical computing | Feb 6, 2020 | Issued |
Array
(
[id] => 16965195
[patent_doc_number] => 20210216694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-15
[patent_title] => Debugging non-detected faults using sequential equivalence checking
[patent_app_type] => utility
[patent_app_number] => 16/873675
[patent_app_country] => US
[patent_app_date] => 2020-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8276
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16873675
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/873675 | Debugging non-detected faults using sequential equivalence checking | Jan 6, 2020 | Abandoned |
Array
(
[id] => 16881228
[patent_doc_number] => 11031385
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-08
[patent_title] => Standard cell for removing routing interference between adjacent pins and device including the same
[patent_app_type] => utility
[patent_app_number] => 16/725023
[patent_app_country] => US
[patent_app_date] => 2019-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 9863
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 384
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725023
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/725023 | Standard cell for removing routing interference between adjacent pins and device including the same | Dec 22, 2019 | Issued |
Array
(
[id] => 17151625
[patent_doc_number] => 11144703
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-10-12
[patent_title] => Smart repeater design for on-route repeater planning for bus
[patent_app_type] => utility
[patent_app_number] => 16/700230
[patent_app_country] => US
[patent_app_date] => 2019-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 12789
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700230
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/700230 | Smart repeater design for on-route repeater planning for bus | Dec 1, 2019 | Issued |
Array
(
[id] => 16872389
[patent_doc_number] => 20210165856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-03
[patent_title] => AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY
[patent_app_type] => utility
[patent_app_number] => 16/699085
[patent_app_country] => US
[patent_app_date] => 2019-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11766
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699085
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/699085 | Automated design closure with abutted hierarchy | Nov 27, 2019 | Issued |
Array
(
[id] => 16078011
[patent_doc_number] => 20200192992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => INFORMATION PROCESSING APPARATUS AND PULL-UP AND PULL-DOWN RESISTOR VERIFICATION METHOD
[patent_app_type] => utility
[patent_app_number] => 16/682228
[patent_app_country] => US
[patent_app_date] => 2019-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20439
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682228
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/682228 | INFORMATION PROCESSING APPARATUS AND PULL-UP AND PULL-DOWN RESISTOR VERIFICATION METHOD | Nov 12, 2019 | Abandoned |
Array
(
[id] => 16826696
[patent_doc_number] => 20210141989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-13
[patent_title] => METHODS OF GENERATING INTEGRATED CIRCUIT (IC) LAYOUT SYNTHETIC PATTERNS AND RELATED COMPUTER PROGRAM PRODUCTS
[patent_app_type] => utility
[patent_app_number] => 16/681082
[patent_app_country] => US
[patent_app_date] => 2019-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8973
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681082
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/681082 | Methods of generating integrated circuit (IC) layout synthetic patterns and related computer program products | Nov 11, 2019 | Issued |
Array
(
[id] => 16943225
[patent_doc_number] => 11055470
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-06
[patent_title] => Optimized electromigration analysis
[patent_app_type] => utility
[patent_app_number] => 16/659134
[patent_app_country] => US
[patent_app_date] => 2019-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4896
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659134
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/659134 | Optimized electromigration analysis | Oct 20, 2019 | Issued |
Array
(
[id] => 16751212
[patent_doc_number] => 20210103221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => TOOL CONTROL USING MULTISTAGE LSTM FOR PREDICTING ON-WAFER MEASUREMENTS
[patent_app_type] => utility
[patent_app_number] => 16/596732
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6078
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596732
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/596732 | Tool control using multistage LSTM for predicting on-wafer measurements | Oct 7, 2019 | Issued |
Array
(
[id] => 15903721
[patent_doc_number] => 20200151380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/571773
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8616
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571773
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571773 | System for placement optimization of chip design for transient noise control and related methods thereof | Sep 15, 2019 | Issued |
Array
(
[id] => 16146275
[patent_doc_number] => 10706209
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-07
[patent_title] => Estimation of effective channel length for FinFETs and nano-wires
[patent_app_type] => utility
[patent_app_number] => 16/568157
[patent_app_country] => US
[patent_app_date] => 2019-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6959
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568157
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/568157 | Estimation of effective channel length for FinFETs and nano-wires | Sep 10, 2019 | Issued |