
Aric Lin
Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 612 |
| Issued Applications | 347 |
| Pending Applications | 60 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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