Search

Aric Lin

Examiner (ID: 4045, Phone: (571)270-3090 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
612
Issued Applications
347
Pending Applications
60
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16872389 [patent_doc_number] => 20210165856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY [patent_app_type] => utility [patent_app_number] => 16/699085 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699085
Automated design closure with abutted hierarchy Nov 27, 2019 Issued
Array ( [id] => 16078011 [patent_doc_number] => 20200192992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => INFORMATION PROCESSING APPARATUS AND PULL-UP AND PULL-DOWN RESISTOR VERIFICATION METHOD [patent_app_type] => utility [patent_app_number] => 16/682228 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682228
INFORMATION PROCESSING APPARATUS AND PULL-UP AND PULL-DOWN RESISTOR VERIFICATION METHOD Nov 12, 2019 Abandoned
Array ( [id] => 16826696 [patent_doc_number] => 20210141989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => METHODS OF GENERATING INTEGRATED CIRCUIT (IC) LAYOUT SYNTHETIC PATTERNS AND RELATED COMPUTER PROGRAM PRODUCTS [patent_app_type] => utility [patent_app_number] => 16/681082 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681082
Methods of generating integrated circuit (IC) layout synthetic patterns and related computer program products Nov 11, 2019 Issued
Array ( [id] => 16943225 [patent_doc_number] => 11055470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Optimized electromigration analysis [patent_app_type] => utility [patent_app_number] => 16/659134 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659134 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/659134
Optimized electromigration analysis Oct 20, 2019 Issued
Array ( [id] => 16751212 [patent_doc_number] => 20210103221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => TOOL CONTROL USING MULTISTAGE LSTM FOR PREDICTING ON-WAFER MEASUREMENTS [patent_app_type] => utility [patent_app_number] => 16/596732 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596732 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596732
Tool control using multistage LSTM for predicting on-wafer measurements Oct 7, 2019 Issued
Array ( [id] => 15903721 [patent_doc_number] => 20200151380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SYSTEM FOR PLACEMENT OPTIMIZATION OF CHIP DESIGN FOR TRANSIENT NOISE CONTROL AND RELATED METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/571773 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571773
System for placement optimization of chip design for transient noise control and related methods thereof Sep 15, 2019 Issued
Array ( [id] => 16146275 [patent_doc_number] => 10706209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Estimation of effective channel length for FinFETs and nano-wires [patent_app_type] => utility [patent_app_number] => 16/568157 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568157 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568157
Estimation of effective channel length for FinFETs and nano-wires Sep 10, 2019 Issued
Array ( [id] => 16146271 [patent_doc_number] => 10706207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Circuit design verification apparatus and program [patent_app_type] => utility [patent_app_number] => 16/502933 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7021 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502933
Circuit design verification apparatus and program Jul 2, 2019 Issued
Array ( [id] => 14873069 [patent_doc_number] => 20190286776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SYSTEM DESIGN USING ACCURATE PERFORMANCE MODELS [patent_app_type] => utility [patent_app_number] => 16/430415 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430415
System design using accurate performance models Jun 2, 2019 Issued
Array ( [id] => 14751203 [patent_doc_number] => 20190258775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION AND A SHIFT [patent_app_type] => utility [patent_app_number] => 16/404910 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404910 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404910
System and method of analyzing integrated circuit in consideration of a process variation and a shift May 6, 2019 Issued
Array ( [id] => 14751195 [patent_doc_number] => 20190258771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE [patent_app_type] => utility [patent_app_number] => 16/400434 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400434
Checking wafer-level integrated designs for rule compliance Apr 30, 2019 Issued
Array ( [id] => 16393151 [patent_doc_number] => 20200334092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SYSTEM AND METHOD FOR IDENTIFYING A CAUSE OF A FAILURE IN OPERATION OF A CHIP [patent_app_type] => utility [patent_app_number] => 16/385848 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/385848
SYSTEM AND METHOD FOR IDENTIFYING A CAUSE OF A FAILURE IN OPERATION OF A CHIP Apr 15, 2019 Abandoned
Array ( [id] => 16987204 [patent_doc_number] => 11074379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Multi-cycle latch tree synthesis [patent_app_type] => utility [patent_app_number] => 16/370948 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 12221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370948
Multi-cycle latch tree synthesis Mar 29, 2019 Issued
Array ( [id] => 16927353 [patent_doc_number] => 11048839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Adaptive error correction in quantum computing [patent_app_type] => utility [patent_app_number] => 16/370062 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9930 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370062
Adaptive error correction in quantum computing Mar 28, 2019 Issued
Array ( [id] => 16346566 [patent_doc_number] => 20200311217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD AND SYSTEM FOR IMPLEMENTING MEMORY CHANGES IN DIGITAL INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/370276 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370276
METHOD AND SYSTEM FOR IMPLEMENTING MEMORY CHANGES IN DIGITAL INTEGRATED CIRCUITS Mar 28, 2019 Abandoned
Array ( [id] => 17801599 [patent_doc_number] => 11415896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Dissection method for layout patterns in semiconductor device, optical proximity correction method including the same and method of manufacturing semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 16/369932 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11573 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369932
Dissection method for layout patterns in semiconductor device, optical proximity correction method including the same and method of manufacturing semiconductor device including the same Mar 28, 2019 Issued
Array ( [id] => 17352450 [patent_doc_number] => 11227089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => System and method for implementing functional logics of verification IP using state design pattern based FSMs [patent_app_type] => utility [patent_app_number] => 16/370615 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6428 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370615
System and method for implementing functional logics of verification IP using state design pattern based FSMs Mar 28, 2019 Issued
Array ( [id] => 20143422 [patent_doc_number] => 12377747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Method to detect vehicle battery type before charge [patent_app_type] => utility [patent_app_number] => 17/279201 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5761 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17279201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/279201
Method to detect vehicle battery type before charge Mar 28, 2019 Issued
Array ( [id] => 16117045 [patent_doc_number] => 20200210545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 16/237995 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237995
CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DESIGNS Jan 1, 2019 Abandoned
Array ( [id] => 15137473 [patent_doc_number] => 10482208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Coding and synthesizing a state machine in state groups [patent_app_type] => utility [patent_app_number] => 16/237657 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 10628 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237657
Coding and synthesizing a state machine in state groups Dec 30, 2018 Issued
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