| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Integrated circuit configuration for reducing current consumption'
[patent_app_type] => 1
[patent_app_number] => 8/841120
[patent_app_country] => US
[patent_app_date] => 1997-04-29
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[firstpage_image] =>[orig_patent_app_number] => 841120
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/841120 | Integrated circuit configuration for reducing current consumption | Apr 28, 1997 | Issued |
Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Method and system for assigning a direct memory access priority in a packetized data communications interface device'
[patent_app_type] => 1
[patent_app_number] => 8/840689
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[pdf_file] => patents/05/983/05983301.pdf
[firstpage_image] =>[orig_patent_app_number] => 840689
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840689 | Method and system for assigning a direct memory access priority in a packetized data communications interface device | Apr 28, 1997 | Issued |
Array
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[patent_doc_number] => 05911054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Single-operation list entry update method in mixed bus environments'
[patent_app_type] => 1
[patent_app_number] => 8/841247
[patent_app_country] => US
[patent_app_date] => 1997-04-29
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[pdf_file] => patents/05/911/05911054.pdf
[firstpage_image] =>[orig_patent_app_number] => 841247
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/841247 | Single-operation list entry update method in mixed bus environments | Apr 28, 1997 | Issued |
Array
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[id] => 3996293
[patent_doc_number] => 05911079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Computer system having a parallel port for its peripheral device and an expansion device thereof'
[patent_app_type] => 1
[patent_app_number] => 8/840631
[patent_app_country] => US
[patent_app_date] => 1997-04-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/911/05911079.pdf
[firstpage_image] =>[orig_patent_app_number] => 840631
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840631 | Computer system having a parallel port for its peripheral device and an expansion device thereof | Apr 24, 1997 | Issued |
Array
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[id] => 4138394
[patent_doc_number] => 06073193
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Fail safe method and apparatus for a USB device'
[patent_app_type] => 1
[patent_app_number] => 8/839981
[patent_app_country] => US
[patent_app_date] => 1997-04-24
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[firstpage_image] =>[orig_patent_app_number] => 839981
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/839981 | Fail safe method and apparatus for a USB device | Apr 23, 1997 | Issued |
Array
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[id] => 3986111
[patent_doc_number] => 05919260
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Electrical apparatus producing direct computer controlled variance in operation of an electrical end device'
[patent_app_type] => 1
[patent_app_number] => 8/840500
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[patent_app_date] => 1997-04-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840500 | Electrical apparatus producing direct computer controlled variance in operation of an electrical end device | Apr 20, 1997 | Issued |
Array
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[id] => 3794067
[patent_doc_number] => 05809261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'System and method for transferring data streams simultaneously on multiple buses in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/826338
[patent_app_country] => US
[patent_app_date] => 1997-03-26
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[pdf_file] => patents/05/809/05809261.pdf
[firstpage_image] =>[orig_patent_app_number] => 826338
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/826338 | System and method for transferring data streams simultaneously on multiple buses in a computer system | Mar 25, 1997 | Issued |
Array
(
[id] => 3798045
[patent_doc_number] => 05809524
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Method and apparatus for cache memory replacement line identification'
[patent_app_type] => 1
[patent_app_number] => 8/822044
[patent_app_country] => US
[patent_app_date] => 1997-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/809/05809524.pdf
[firstpage_image] =>[orig_patent_app_number] => 822044
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/822044 | Method and apparatus for cache memory replacement line identification | Mar 23, 1997 | Issued |
Array
(
[id] => 3849634
[patent_doc_number] => 05761463
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Method and apparatus for logic network interfacing with automatic receiver node and transmit node selection capability'
[patent_app_type] => 1
[patent_app_number] => 8/808193
[patent_app_country] => US
[patent_app_date] => 1997-02-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/761/05761463.pdf
[firstpage_image] =>[orig_patent_app_number] => 808193
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/808193 | Method and apparatus for logic network interfacing with automatic receiver node and transmit node selection capability | Feb 27, 1997 | Issued |
| 08/791261 | STORAGE APPARATUS | Jan 29, 1997 | Abandoned |
Array
(
[id] => 4426952
[patent_doc_number] => 06195754
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[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Method and apparatus for tolerating power outages of variable duration in a multi-processor system'
[patent_app_type] => 1
[patent_app_number] => 8/789260
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Array
(
[id] => 3794352
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[patent_issue_date] => 1998-09-15
[patent_title] => 'Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM'
[patent_app_type] => 1
[patent_app_number] => 8/790271
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[pdf_file] => patents/05/809/05809281.pdf
[firstpage_image] =>[orig_patent_app_number] => 790271
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/790271 | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM | Jan 27, 1997 | Issued |
Array
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[patent_issue_date] => 1999-10-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/770945 | System and method of positively determining ISA cycle claiming | Dec 30, 1996 | Issued |
Array
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[patent_issue_date] => 1999-09-07
[patent_title] => 'Bus interface unit for preventing deadlock'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/773562 | Bus interface unit for preventing deadlock | Dec 26, 1996 | Issued |
Array
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[patent_issue_date] => 1999-07-13
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[firstpage_image] =>[orig_patent_app_number] => 772163
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772163 | Power management control of pointing devices during low-power states | Dec 19, 1996 | Issued |
Array
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[id] => 3807623
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/766363 | Apparatus and method for page migration in a non-uniform memory access (NUMA) system | Dec 16, 1996 | Issued |
Array
(
[id] => 4148502
[patent_doc_number] => 06016518
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Automatic master/slave designation for computer peripherals'
[patent_app_type] => 1
[patent_app_number] => 8/753854
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[patent_app_date] => 1996-12-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/753854 | Automatic master/slave designation for computer peripherals | Dec 2, 1996 | Issued |
| 08/750186 | PERFORMING INPUT/OUTPUT OPERATIONS IN A MULTIPROCESSOR SYSTEM | Dec 2, 1996 | Abandoned |
Array
(
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Array
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