Search

Ario Etienne

Supervisory Patent Examiner (ID: 13470, Phone: (571)272-4001 , Office: P/2457 )

Most Active Art Unit
2781
Art Unit(s)
2457, 2781, 2155, 2157, 2312, 2305, 2787
Total Applications
502
Issued Applications
404
Pending Applications
51
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3936031 [patent_doc_number] => 05915121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Integrated circuit configuration for reducing current consumption' [patent_app_type] => 1 [patent_app_number] => 8/841120 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1574 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915121.pdf [firstpage_image] =>[orig_patent_app_number] => 841120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841120
Integrated circuit configuration for reducing current consumption Apr 28, 1997 Issued
Array ( [id] => 3966972 [patent_doc_number] => 05983301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method and system for assigning a direct memory access priority in a packetized data communications interface device' [patent_app_type] => 1 [patent_app_number] => 8/840689 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 18753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983301.pdf [firstpage_image] =>[orig_patent_app_number] => 840689 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840689
Method and system for assigning a direct memory access priority in a packetized data communications interface device Apr 28, 1997 Issued
Array ( [id] => 3995891 [patent_doc_number] => 05911054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Single-operation list entry update method in mixed bus environments' [patent_app_type] => 1 [patent_app_number] => 8/841247 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2663 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911054.pdf [firstpage_image] =>[orig_patent_app_number] => 841247 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841247
Single-operation list entry update method in mixed bus environments Apr 28, 1997 Issued
Array ( [id] => 3996293 [patent_doc_number] => 05911079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Computer system having a parallel port for its peripheral device and an expansion device thereof' [patent_app_type] => 1 [patent_app_number] => 8/840631 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5399 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911079.pdf [firstpage_image] =>[orig_patent_app_number] => 840631 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840631
Computer system having a parallel port for its peripheral device and an expansion device thereof Apr 24, 1997 Issued
Array ( [id] => 4138394 [patent_doc_number] => 06073193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Fail safe method and apparatus for a USB device' [patent_app_type] => 1 [patent_app_number] => 8/839981 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073193.pdf [firstpage_image] =>[orig_patent_app_number] => 839981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839981
Fail safe method and apparatus for a USB device Apr 23, 1997 Issued
Array ( [id] => 3986111 [patent_doc_number] => 05919260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Electrical apparatus producing direct computer controlled variance in operation of an electrical end device' [patent_app_type] => 1 [patent_app_number] => 8/840500 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4627 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/919/05919260.pdf [firstpage_image] =>[orig_patent_app_number] => 840500 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840500
Electrical apparatus producing direct computer controlled variance in operation of an electrical end device Apr 20, 1997 Issued
Array ( [id] => 3794067 [patent_doc_number] => 05809261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'System and method for transferring data streams simultaneously on multiple buses in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/826338 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 16231 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809261.pdf [firstpage_image] =>[orig_patent_app_number] => 826338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826338
System and method for transferring data streams simultaneously on multiple buses in a computer system Mar 25, 1997 Issued
Array ( [id] => 3798045 [patent_doc_number] => 05809524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method and apparatus for cache memory replacement line identification' [patent_app_type] => 1 [patent_app_number] => 8/822044 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9982 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809524.pdf [firstpage_image] =>[orig_patent_app_number] => 822044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822044
Method and apparatus for cache memory replacement line identification Mar 23, 1997 Issued
Array ( [id] => 3849634 [patent_doc_number] => 05761463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and apparatus for logic network interfacing with automatic receiver node and transmit node selection capability' [patent_app_type] => 1 [patent_app_number] => 8/808193 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4444 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761463.pdf [firstpage_image] =>[orig_patent_app_number] => 808193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808193
Method and apparatus for logic network interfacing with automatic receiver node and transmit node selection capability Feb 27, 1997 Issued
08/791261 STORAGE APPARATUS Jan 29, 1997 Abandoned
Array ( [id] => 4426952 [patent_doc_number] => 06195754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method and apparatus for tolerating power outages of variable duration in a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 8/789260 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 12484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195754.pdf [firstpage_image] =>[orig_patent_app_number] => 789260 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789260
Method and apparatus for tolerating power outages of variable duration in a multi-processor system Jan 27, 1997 Issued
Array ( [id] => 3794352 [patent_doc_number] => 05809281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM' [patent_app_type] => 1 [patent_app_number] => 8/790271 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 6689 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809281.pdf [firstpage_image] =>[orig_patent_app_number] => 790271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790271
Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM Jan 27, 1997 Issued
Array ( [id] => 4036695 [patent_doc_number] => 05968151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'System and method of positively determining ISA cycle claiming' [patent_app_type] => 1 [patent_app_number] => 8/770945 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5408 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968151.pdf [firstpage_image] =>[orig_patent_app_number] => 770945 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770945
System and method of positively determining ISA cycle claiming Dec 30, 1996 Issued
Array ( [id] => 3997938 [patent_doc_number] => 05949980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Bus interface unit for preventing deadlock' [patent_app_type] => 1 [patent_app_number] => 8/773562 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3023 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949980.pdf [firstpage_image] =>[orig_patent_app_number] => 773562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773562
Bus interface unit for preventing deadlock Dec 26, 1996 Issued
Array ( [id] => 3987821 [patent_doc_number] => 05922075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Power management control of pointing devices during low-power states' [patent_app_type] => 1 [patent_app_number] => 8/772163 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2337 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/922/05922075.pdf [firstpage_image] =>[orig_patent_app_number] => 772163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772163
Power management control of pointing devices during low-power states Dec 19, 1996 Issued
Array ( [id] => 3807623 [patent_doc_number] => 05727150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Apparatus and method for page migration in a non-uniform memory access (NUMA) system' [patent_app_type] => 1 [patent_app_number] => 8/766363 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5123 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727150.pdf [firstpage_image] =>[orig_patent_app_number] => 766363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766363
Apparatus and method for page migration in a non-uniform memory access (NUMA) system Dec 16, 1996 Issued
Array ( [id] => 4148502 [patent_doc_number] => 06016518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Automatic master/slave designation for computer peripherals' [patent_app_type] => 1 [patent_app_number] => 8/753854 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5549 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016518.pdf [firstpage_image] =>[orig_patent_app_number] => 753854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753854
Automatic master/slave designation for computer peripherals Dec 2, 1996 Issued
08/750186 PERFORMING INPUT/OUTPUT OPERATIONS IN A MULTIPROCESSOR SYSTEM Dec 2, 1996 Abandoned
Array ( [id] => 3831009 [patent_doc_number] => 05812874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Equipment management system' [patent_app_type] => 1 [patent_app_number] => 8/757505 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4487 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812874.pdf [firstpage_image] =>[orig_patent_app_number] => 757505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757505
Equipment management system Nov 26, 1996 Issued
Array ( [id] => 3984585 [patent_doc_number] => 05887191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'System and method for bounding response time jitter for high priority commands in a multimedia datastreaming system' [patent_app_type] => 1 [patent_app_number] => 8/753565 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7767 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887191.pdf [firstpage_image] =>[orig_patent_app_number] => 753565 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753565
System and method for bounding response time jitter for high priority commands in a multimedia datastreaming system Nov 25, 1996 Issued
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