Search

Ario Etienne

Supervisory Patent Examiner (ID: 13470, Phone: (571)272-4001 , Office: P/2457 )

Most Active Art Unit
2781
Art Unit(s)
2457, 2781, 2155, 2157, 2312, 2305, 2787
Total Applications
502
Issued Applications
404
Pending Applications
51
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3836209 [patent_doc_number] => 05790816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Apparatus for transferring information from a bus to a network without the use of protocol engines' [patent_app_type] => 1 [patent_app_number] => 8/711093 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1114 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790816.pdf [firstpage_image] =>[orig_patent_app_number] => 711093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711093
Apparatus for transferring information from a bus to a network without the use of protocol engines Sep 8, 1996 Issued
Array ( [id] => 3878514 [patent_doc_number] => 05794000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method and apparatus for avoiding erroneous abort occurrences in PCI-bus systems' [patent_app_type] => 1 [patent_app_number] => 8/707962 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4634 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/794/05794000.pdf [firstpage_image] =>[orig_patent_app_number] => 707962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707962
Method and apparatus for avoiding erroneous abort occurrences in PCI-bus systems Aug 29, 1996 Issued
Array ( [id] => 3844190 [patent_doc_number] => 05713003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method and system for caching data' [patent_app_type] => 1 [patent_app_number] => 8/705517 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4982 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/713/05713003.pdf [firstpage_image] =>[orig_patent_app_number] => 705517 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705517
Method and system for caching data Aug 28, 1996 Issued
Array ( [id] => 3849489 [patent_doc_number] => 05761454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Deadlock resolution methods and apparatus for interfacing concurrent and asynchronous buses' [patent_app_type] => 1 [patent_app_number] => 8/703563 [patent_app_country] => US [patent_app_date] => 1996-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6965 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761454.pdf [firstpage_image] =>[orig_patent_app_number] => 703563 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703563
Deadlock resolution methods and apparatus for interfacing concurrent and asynchronous buses Aug 26, 1996 Issued
Array ( [id] => 3952286 [patent_doc_number] => 05872982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Reducing the elapsed time period between an interrupt acknowledge and an interrupt vector' [patent_app_type] => 1 [patent_app_number] => 8/688555 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3381 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872982.pdf [firstpage_image] =>[orig_patent_app_number] => 688555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/688555
Reducing the elapsed time period between an interrupt acknowledge and an interrupt vector Jul 29, 1996 Issued
Array ( [id] => 3939839 [patent_doc_number] => 05954809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Circuit for handling distributed arbitration in a computer system having multiple arbiters' [patent_app_type] => 1 [patent_app_number] => 8/684412 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11552 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954809.pdf [firstpage_image] =>[orig_patent_app_number] => 684412 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684412
Circuit for handling distributed arbitration in a computer system having multiple arbiters Jul 18, 1996 Issued
Array ( [id] => 3879317 [patent_doc_number] => 05794054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Flash ROM sharing between a processor and a controller' [patent_app_type] => 1 [patent_app_number] => 8/684414 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8514 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/794/05794054.pdf [firstpage_image] =>[orig_patent_app_number] => 684414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684414
Flash ROM sharing between a processor and a controller Jul 18, 1996 Issued
Array ( [id] => 3952307 [patent_doc_number] => 05872983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Power management interface system for use with an electronic wiring board article of manufacture' [patent_app_type] => 1 [patent_app_number] => 8/682462 [patent_app_country] => US [patent_app_date] => 1996-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 73 [patent_no_of_words] => 92768 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872983.pdf [firstpage_image] =>[orig_patent_app_number] => 682462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/682462
Power management interface system for use with an electronic wiring board article of manufacture Jul 16, 1996 Issued
Array ( [id] => 3812145 [patent_doc_number] => 05781780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Power management supply interface circuitry, systems and methods' [patent_app_type] => 1 [patent_app_number] => 8/682460 [patent_app_country] => US [patent_app_date] => 1996-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 73 [patent_no_of_words] => 92691 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781780.pdf [firstpage_image] =>[orig_patent_app_number] => 682460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/682460
Power management supply interface circuitry, systems and methods Jul 16, 1996 Issued
Array ( [id] => 3995814 [patent_doc_number] => 05911049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'PCI connection system for a printer controller board' [patent_app_type] => 1 [patent_app_number] => 8/679565 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6489 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911049.pdf [firstpage_image] =>[orig_patent_app_number] => 679565 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679565
PCI connection system for a printer controller board Jul 14, 1996 Issued
Array ( [id] => 3847769 [patent_doc_number] => 05740380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and system for apportioning computer bus bandwidth' [patent_app_type] => 1 [patent_app_number] => 8/680464 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5025 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740380.pdf [firstpage_image] =>[orig_patent_app_number] => 680464 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680464
Method and system for apportioning computer bus bandwidth Jul 14, 1996 Issued
Array ( [id] => 3897219 [patent_doc_number] => 05805839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Efficient technique for implementing broadcasts on a system of hierarchical buses' [patent_app_type] => 1 [patent_app_number] => 8/675362 [patent_app_country] => US [patent_app_date] => 1996-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12205 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805839.pdf [firstpage_image] =>[orig_patent_app_number] => 675362 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675362
Efficient technique for implementing broadcasts on a system of hierarchical buses Jul 1, 1996 Issued
Array ( [id] => 3893431 [patent_doc_number] => 05764896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and system for reducing transfer latency when transferring data from a network to a computer system' [patent_app_type] => 1 [patent_app_number] => 8/671583 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 6047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764896.pdf [firstpage_image] =>[orig_patent_app_number] => 671583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671583
Method and system for reducing transfer latency when transferring data from a network to a computer system Jun 27, 1996 Issued
Array ( [id] => 3984369 [patent_doc_number] => 05887177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Host-controlled power management of a computer sound system' [patent_app_type] => 1 [patent_app_number] => 8/671961 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 5413 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887177.pdf [firstpage_image] =>[orig_patent_app_number] => 671961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671961
Host-controlled power management of a computer sound system Jun 27, 1996 Issued
Array ( [id] => 4057815 [patent_doc_number] => 05875345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Information processing system having dual power saving modes' [patent_app_type] => 1 [patent_app_number] => 8/673412 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6556 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875345.pdf [firstpage_image] =>[orig_patent_app_number] => 673412 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673412
Information processing system having dual power saving modes Jun 27, 1996 Issued
Array ( [id] => 3784270 [patent_doc_number] => 05734841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Circuit for plug/play in peripheral component interconnect bus' [patent_app_type] => 1 [patent_app_number] => 8/668362 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2155 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734841.pdf [firstpage_image] =>[orig_patent_app_number] => 668362 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668362
Circuit for plug/play in peripheral component interconnect bus Jun 25, 1996 Issued
Array ( [id] => 3716123 [patent_doc_number] => 05681285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Infusion pump with an electronically loadable drug library and a user interface for loading the library' [patent_app_type] => 1 [patent_app_number] => 8/665828 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 16964 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681285.pdf [firstpage_image] =>[orig_patent_app_number] => 665828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665828
Infusion pump with an electronically loadable drug library and a user interface for loading the library Jun 18, 1996 Issued
Array ( [id] => 3878397 [patent_doc_number] => 05793992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method and apparatus for arbitrating access to main memory of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/664107 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8056 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793992.pdf [firstpage_image] =>[orig_patent_app_number] => 664107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664107
Method and apparatus for arbitrating access to main memory of a computer system Jun 12, 1996 Issued
Array ( [id] => 4081997 [patent_doc_number] => 05867719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and apparatus for testing on-chip memory on a microcontroller' [patent_app_type] => 1 [patent_app_number] => 8/669863 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2551 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867719.pdf [firstpage_image] =>[orig_patent_app_number] => 669863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/669863
Method and apparatus for testing on-chip memory on a microcontroller Jun 9, 1996 Issued
Array ( [id] => 3995907 [patent_doc_number] => 05911055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Using subordinate bus devices that are connected to a common bus' [patent_app_type] => 1 [patent_app_number] => 8/658634 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 127 [patent_figures_cnt] => 136 [patent_no_of_words] => 71164 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911055.pdf [firstpage_image] =>[orig_patent_app_number] => 658634 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658634
Using subordinate bus devices that are connected to a common bus Jun 4, 1996 Issued
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