Search

Ario Etienne

Supervisory Patent Examiner (ID: 13470, Phone: (571)272-4001 , Office: P/2457 )

Most Active Art Unit
2781
Art Unit(s)
2457, 2781, 2155, 2157, 2312, 2305, 2787
Total Applications
502
Issued Applications
404
Pending Applications
51
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3898219 [patent_doc_number] => 05805903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Protection of computer system against incorrect card insertion during start-up' [patent_app_type] => 1 [patent_app_number] => 8/651049 [patent_app_country] => US [patent_app_date] => 1996-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5691 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805903.pdf [firstpage_image] =>[orig_patent_app_number] => 651049 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651049
Protection of computer system against incorrect card insertion during start-up May 20, 1996 Issued
Array ( [id] => 3813049 [patent_doc_number] => 05828853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method and apparatus for interfacing two systems operating in potentially differing Endian modes' [patent_app_type] => 1 [patent_app_number] => 8/646563 [patent_app_country] => US [patent_app_date] => 1996-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3762 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828853.pdf [firstpage_image] =>[orig_patent_app_number] => 646563 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/646563
Method and apparatus for interfacing two systems operating in potentially differing Endian modes May 7, 1996 Issued
Array ( [id] => 3850392 [patent_doc_number] => 05761516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Single chip multiprocessor architecture with internal task switching synchronization bus' [patent_app_type] => 1 [patent_app_number] => 8/643263 [patent_app_country] => US [patent_app_date] => 1996-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4294 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761516.pdf [firstpage_image] =>[orig_patent_app_number] => 643263 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643263
Single chip multiprocessor architecture with internal task switching synchronization bus May 2, 1996 Issued
Array ( [id] => 3813020 [patent_doc_number] => 05828851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Process control system using standard protocol control of standard devices and nonstandard devices' [patent_app_type] => 1 [patent_app_number] => 8/631862 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 16455 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828851.pdf [firstpage_image] =>[orig_patent_app_number] => 631862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/631862
Process control system using standard protocol control of standard devices and nonstandard devices Apr 11, 1996 Issued
Array ( [id] => 3901776 [patent_doc_number] => 05715467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Event driven power management control circuit and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/627461 [patent_app_country] => US [patent_app_date] => 1996-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2021 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715467.pdf [firstpage_image] =>[orig_patent_app_number] => 627461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627461
Event driven power management control circuit and method therefor Apr 3, 1996 Issued
Array ( [id] => 3738383 [patent_doc_number] => 05652856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Memory controller having all DRAM address and control singals provided synchronously from a single device' [patent_app_type] => 1 [patent_app_number] => 8/611247 [patent_app_country] => US [patent_app_date] => 1996-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 78 [patent_no_of_words] => 29652 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652856.pdf [firstpage_image] =>[orig_patent_app_number] => 611247 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611247
Memory controller having all DRAM address and control singals provided synchronously from a single device Mar 4, 1996 Issued
Array ( [id] => 3872961 [patent_doc_number] => 05768599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Interrupt managing system for real-time operating system' [patent_app_type] => 1 [patent_app_number] => 8/607461 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4951 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768599.pdf [firstpage_image] =>[orig_patent_app_number] => 607461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607461
Interrupt managing system for real-time operating system Feb 26, 1996 Issued
Array ( [id] => 3708858 [patent_doc_number] => 05680643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Data bus including address request line for allowing request for a subsequent address word during a burst mode transfer' [patent_app_type] => 1 [patent_app_number] => 8/591588 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3722 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680643.pdf [firstpage_image] =>[orig_patent_app_number] => 591588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/591588
Data bus including address request line for allowing request for a subsequent address word during a burst mode transfer Feb 8, 1996 Issued
Array ( [id] => 3915383 [patent_doc_number] => 05944807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Compact ISA-bus interface' [patent_app_type] => 1 [patent_app_number] => 8/595989 [patent_app_country] => US [patent_app_date] => 1996-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7340 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944807.pdf [firstpage_image] =>[orig_patent_app_number] => 595989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/595989
Compact ISA-bus interface Feb 5, 1996 Issued
Array ( [id] => 3898172 [patent_doc_number] => 05748910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Automatic enabling/disabling of termination impedance for a computer bus' [patent_app_type] => 1 [patent_app_number] => 8/594190 [patent_app_country] => US [patent_app_date] => 1996-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 1988 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748910.pdf [firstpage_image] =>[orig_patent_app_number] => 594190 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/594190
Automatic enabling/disabling of termination impedance for a computer bus Jan 30, 1996 Issued
Array ( [id] => 3841537 [patent_doc_number] => 05784578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and system for enhancing the efficiency of data communication between a terminal device and a host computer having an optimizer' [patent_app_type] => 1 [patent_app_number] => 8/588664 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5918 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784578.pdf [firstpage_image] =>[orig_patent_app_number] => 588664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/588664
Method and system for enhancing the efficiency of data communication between a terminal device and a host computer having an optimizer Jan 16, 1996 Issued
Array ( [id] => 3897136 [patent_doc_number] => 05805833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method and apparatus for replicating peripheral device ports in an expansion unit' [patent_app_type] => 1 [patent_app_number] => 8/587163 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3459 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805833.pdf [firstpage_image] =>[orig_patent_app_number] => 587163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/587163
Method and apparatus for replicating peripheral device ports in an expansion unit Jan 15, 1996 Issued
Array ( [id] => 3900872 [patent_doc_number] => 05715411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Apparatus and method of converting subtractive decode device cycles to positive peripheral component interface decode device cycles' [patent_app_type] => 1 [patent_app_number] => 8/587164 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3546 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715411.pdf [firstpage_image] =>[orig_patent_app_number] => 587164 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/587164
Apparatus and method of converting subtractive decode device cycles to positive peripheral component interface decode device cycles Jan 15, 1996 Issued
Array ( [id] => 3935989 [patent_doc_number] => 05915118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Apparatus and method for gradually shutting down a power supply' [patent_app_type] => 1 [patent_app_number] => 8/585689 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5899 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915118.pdf [firstpage_image] =>[orig_patent_app_number] => 585689 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/585689
Apparatus and method for gradually shutting down a power supply Jan 15, 1996 Issued
Array ( [id] => 3899033 [patent_doc_number] => 05748968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Requesting device capable of canceling its memory access requests upon detecting other specific requesting devices simultaneously asserting access requests' [patent_app_type] => 1 [patent_app_number] => 8/583390 [patent_app_country] => US [patent_app_date] => 1996-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2884 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748968.pdf [firstpage_image] =>[orig_patent_app_number] => 583390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/583390
Requesting device capable of canceling its memory access requests upon detecting other specific requesting devices simultaneously asserting access requests Jan 4, 1996 Issued
Array ( [id] => 3701962 [patent_doc_number] => 05692202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'System, apparatus, and method for managing power in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/581164 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4557 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692202.pdf [firstpage_image] =>[orig_patent_app_number] => 581164 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581164
System, apparatus, and method for managing power in a computer system Dec 28, 1995 Issued
Array ( [id] => 3803253 [patent_doc_number] => 05822595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method and apparatus for providing an interrupt handler employing a token window scheme' [patent_app_type] => 1 [patent_app_number] => 8/581463 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6341 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822595.pdf [firstpage_image] =>[orig_patent_app_number] => 581463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581463
Method and apparatus for providing an interrupt handler employing a token window scheme Dec 28, 1995 Issued
Array ( [id] => 3850616 [patent_doc_number] => 05761532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Direct memory access controller with interface configured to generate wait states' [patent_app_type] => 1 [patent_app_number] => 8/581163 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3610 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761532.pdf [firstpage_image] =>[orig_patent_app_number] => 581163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581163
Direct memory access controller with interface configured to generate wait states Dec 28, 1995 Issued
Array ( [id] => 3741553 [patent_doc_number] => 05671375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method for communicating between a microprocessor and an interface circuit' [patent_app_type] => 1 [patent_app_number] => 8/578763 [patent_app_country] => US [patent_app_date] => 1995-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5135 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671375.pdf [firstpage_image] =>[orig_patent_app_number] => 578763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/578763
Method for communicating between a microprocessor and an interface circuit Dec 25, 1995 Issued
Array ( [id] => 3734093 [patent_doc_number] => 05682484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'System and method for transferring data streams simultaneously on multiple buses in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/559664 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 16233 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682484.pdf [firstpage_image] =>[orig_patent_app_number] => 559664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559664
System and method for transferring data streams simultaneously on multiple buses in a computer system Nov 19, 1995 Issued
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