Search

Ario Etienne

Supervisory Patent Examiner (ID: 13470, Phone: (571)272-4001 , Office: P/2457 )

Most Active Art Unit
2781
Art Unit(s)
2457, 2781, 2155, 2157, 2312, 2305, 2787
Total Applications
502
Issued Applications
404
Pending Applications
51
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4056882 [patent_doc_number] => 05909557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Integrated circuit with programmable bus configuration' [patent_app_type] => 1 [patent_app_number] => 8/559868 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3009 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909557.pdf [firstpage_image] =>[orig_patent_app_number] => 559868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559868
Integrated circuit with programmable bus configuration Nov 19, 1995 Issued
Array ( [id] => 3807948 [patent_doc_number] => 05727171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices' [patent_app_type] => 1 [patent_app_number] => 8/558511 [patent_app_country] => US [patent_app_date] => 1995-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11031 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727171.pdf [firstpage_image] =>[orig_patent_app_number] => 558511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/558511
Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices Nov 15, 1995 Issued
Array ( [id] => 3839111 [patent_doc_number] => 05732225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Integrated circuit timer system having a global bus for transferring information between local buses' [patent_app_type] => 1 [patent_app_number] => 8/555964 [patent_app_country] => US [patent_app_date] => 1995-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 40 [patent_no_of_words] => 27511 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732225.pdf [firstpage_image] =>[orig_patent_app_number] => 555964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/555964
Integrated circuit timer system having a global bus for transferring information between local buses Nov 12, 1995 Issued
Array ( [id] => 3700870 [patent_doc_number] => 05664121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Dual mode arbitration apparatus and method for reducing latency by allowing the possibility of simultaneous request and access for a shared bus' [patent_app_type] => 1 [patent_app_number] => 8/551862 [patent_app_country] => US [patent_app_date] => 1995-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1755 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664121.pdf [firstpage_image] =>[orig_patent_app_number] => 551862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/551862
Dual mode arbitration apparatus and method for reducing latency by allowing the possibility of simultaneous request and access for a shared bus Nov 6, 1995 Issued
Array ( [id] => 3717170 [patent_doc_number] => 05675813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'System and method for power control in a universal serial bus' [patent_app_type] => 1 [patent_app_number] => 8/548562 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8947 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675813.pdf [firstpage_image] =>[orig_patent_app_number] => 548562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548562
System and method for power control in a universal serial bus Oct 25, 1995 Issued
Array ( [id] => 3854338 [patent_doc_number] => 05708777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Method and apparatus for selectively locking a system password of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/543469 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2605 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708777.pdf [firstpage_image] =>[orig_patent_app_number] => 543469 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543469
Method and apparatus for selectively locking a system password of a computer system Oct 15, 1995 Issued
Array ( [id] => 3844615 [patent_doc_number] => 05713030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Thermal management device and method for a computer processor' [patent_app_type] => 1 [patent_app_number] => 8/540714 [patent_app_country] => US [patent_app_date] => 1995-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4057 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/713/05713030.pdf [firstpage_image] =>[orig_patent_app_number] => 540714 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540714
Thermal management device and method for a computer processor Oct 10, 1995 Issued
Array ( [id] => 3826778 [patent_doc_number] => 05832280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Method and system in a data processing system for interfacing an operating system with a power management controller.' [patent_app_type] => 1 [patent_app_number] => 8/539658 [patent_app_country] => US [patent_app_date] => 1995-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5257 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832280.pdf [firstpage_image] =>[orig_patent_app_number] => 539658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539658
Method and system in a data processing system for interfacing an operating system with a power management controller. Oct 4, 1995 Issued
Array ( [id] => 3700935 [patent_doc_number] => 05692134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Preserving configuration information in a SCAM based SCSI system' [patent_app_type] => 1 [patent_app_number] => 8/532919 [patent_app_country] => US [patent_app_date] => 1995-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4386 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692134.pdf [firstpage_image] =>[orig_patent_app_number] => 532919 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/532919
Preserving configuration information in a SCAM based SCSI system Sep 21, 1995 Issued
Array ( [id] => 3785298 [patent_doc_number] => 05734909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Method for controlling the locking and unlocking of system resources in a shared resource distributed computing environment' [patent_app_type] => 1 [patent_app_number] => 8/522689 [patent_app_country] => US [patent_app_date] => 1995-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734909.pdf [firstpage_image] =>[orig_patent_app_number] => 522689 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522689
Method for controlling the locking and unlocking of system resources in a shared resource distributed computing environment Aug 31, 1995 Issued
Array ( [id] => 3847754 [patent_doc_number] => 05740379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method for generating unique addresses for electrical devices from input bit patterns being verifiable for admissibility' [patent_app_type] => 1 [patent_app_number] => 8/515481 [patent_app_country] => US [patent_app_date] => 1995-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1314 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740379.pdf [firstpage_image] =>[orig_patent_app_number] => 515481 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/515481
Method for generating unique addresses for electrical devices from input bit patterns being verifiable for admissibility Aug 14, 1995 Issued
Array ( [id] => 3673572 [patent_doc_number] => 05649175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method and apparatus for acquiring bus transaction address and command information with no more than zero-hold-time and with fast device acknowledgement' [patent_app_type] => 1 [patent_app_number] => 8/513375 [patent_app_country] => US [patent_app_date] => 1995-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6392 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649175.pdf [firstpage_image] =>[orig_patent_app_number] => 513375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/513375
Method and apparatus for acquiring bus transaction address and command information with no more than zero-hold-time and with fast device acknowledgement Aug 9, 1995 Issued
Array ( [id] => 4299358 [patent_doc_number] => 06282662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Power management override for portable computers' [patent_app_type] => 1 [patent_app_number] => 9/562360 [patent_app_country] => US [patent_app_date] => 1995-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2070 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282662.pdf [firstpage_image] =>[orig_patent_app_number] => 562360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562360
Power management override for portable computers Aug 3, 1995 Issued
Array ( [id] => 3825304 [patent_doc_number] => 05710930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Apparatus and a method for allowing an operating system of a computer system to persist across a power off and on cycle' [patent_app_type] => 1 [patent_app_number] => 8/511263 [patent_app_country] => US [patent_app_date] => 1995-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3911 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710930.pdf [firstpage_image] =>[orig_patent_app_number] => 511263 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/511263
Apparatus and a method for allowing an operating system of a computer system to persist across a power off and on cycle Aug 3, 1995 Issued
Array ( [id] => 3738202 [patent_doc_number] => 05652844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Flexible pin configuration for use in a data processing system during a reset operation and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/494461 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11194 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652844.pdf [firstpage_image] =>[orig_patent_app_number] => 494461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/494461
Flexible pin configuration for use in a data processing system during a reset operation and method therefor Jun 25, 1995 Issued
Array ( [id] => 3672763 [patent_doc_number] => 05649123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'GPIB system with improved parallel poll response detection' [patent_app_type] => 1 [patent_app_number] => 8/472626 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 12507 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649123.pdf [firstpage_image] =>[orig_patent_app_number] => 472626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472626
GPIB system with improved parallel poll response detection Jun 6, 1995 Issued
Array ( [id] => 3735937 [patent_doc_number] => 05673412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Disk system and power-on sequence for the same' [patent_app_type] => 1 [patent_app_number] => 8/472460 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 10710 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673412.pdf [firstpage_image] =>[orig_patent_app_number] => 472460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472460
Disk system and power-on sequence for the same Jun 6, 1995 Issued
Array ( [id] => 3802563 [patent_doc_number] => 05737535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Flow control circuit for networked communications system including arrangement for reducing overhead at the beginning of a communications session by enabling message transmission before receiving flow control information' [patent_app_type] => 1 [patent_app_number] => 8/484460 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6838 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737535.pdf [firstpage_image] =>[orig_patent_app_number] => 484460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/484460
Flow control circuit for networked communications system including arrangement for reducing overhead at the beginning of a communications session by enabling message transmission before receiving flow control information Jun 6, 1995 Issued
Array ( [id] => 3797219 [patent_doc_number] => 05758174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Computer system having a plurality of stored system capability states from which to resume' [patent_app_type] => 1 [patent_app_number] => 8/483330 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 30 [patent_no_of_words] => 43038 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758174.pdf [firstpage_image] =>[orig_patent_app_number] => 483330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483330
Computer system having a plurality of stored system capability states from which to resume Jun 6, 1995 Issued
08/487195 METHOD AND APPARATUS FOR PROCESSING A DIGITAL SIGNAL AND A METHOD FOR READING A DATA FROM MEMORY CELL Jun 6, 1995 Abandoned
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