Search

Ario Etienne

Supervisory Patent Examiner (ID: 13470, Phone: (571)272-4001 , Office: P/2457 )

Most Active Art Unit
2781
Art Unit(s)
2457, 2781, 2155, 2157, 2312, 2305, 2787
Total Applications
502
Issued Applications
404
Pending Applications
51
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
08/435464 APPARATUS AND METHOD FOR PAGE MIGRATION IN A NON-UNIFORM MEMORY ACCESS (NUMA) SYSTEM May 4, 1995 Abandoned
Array ( [id] => 3636517 [patent_doc_number] => 05603001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Semiconductor disk system having a plurality of flash memories' [patent_app_type] => 1 [patent_app_number] => 8/435854 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 47 [patent_no_of_words] => 26216 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603001.pdf [firstpage_image] =>[orig_patent_app_number] => 435854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435854
Semiconductor disk system having a plurality of flash memories May 4, 1995 Issued
08/433915 AUTO TERMINATION OF PLURAL MULTI-CONNECTORS May 1, 1995 Abandoned
08/414364 METHOD AND APPARATUS FOR MINIMIZING POWER CONSUMPTION IN A MICROPROCESSOR CONTROLLED STORAGE DEVICE Mar 30, 1995 Abandoned
Array ( [id] => 3746031 [patent_doc_number] => 05694617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation' [patent_app_type] => 1 [patent_app_number] => 8/414975 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4280 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694617.pdf [firstpage_image] =>[orig_patent_app_number] => 414975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/414975
System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation Mar 30, 1995 Issued
08/412801 POWER DISTRIBUTION FROM A COMPUTER HOST TO A PERIPHERAL UNIT Mar 28, 1995 Abandoned
Array ( [id] => 3762755 [patent_doc_number] => 05802390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Data bus circuit and method of changing over termination resistor of the data bus circuit' [patent_app_type] => 1 [patent_app_number] => 8/411461 [patent_app_country] => US [patent_app_date] => 1995-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6182 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802390.pdf [firstpage_image] =>[orig_patent_app_number] => 411461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/411461
Data bus circuit and method of changing over termination resistor of the data bus circuit Mar 27, 1995 Issued
Array ( [id] => 4111301 [patent_doc_number] => 06126332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Apparatus and method for automatically disconnecting address and data buses in a multimedia system when docking with a portable personal computer' [patent_app_type] => 1 [patent_app_number] => 8/411379 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 144 [patent_figures_cnt] => 197 [patent_no_of_words] => 43921 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/126/06126332.pdf [firstpage_image] =>[orig_patent_app_number] => 411379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/411379
Apparatus and method for automatically disconnecting address and data buses in a multimedia system when docking with a portable personal computer Mar 23, 1995 Issued
Array ( [id] => 3765055 [patent_doc_number] => 05802542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Information management system for a dynamic system and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/409444 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3854 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802542.pdf [firstpage_image] =>[orig_patent_app_number] => 409444 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/409444
Information management system for a dynamic system and method thereof Mar 23, 1995 Issued
Array ( [id] => 3642756 [patent_doc_number] => 05687387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Enhanced active port replicator having expansion and upgrade capabilities' [patent_app_type] => 1 [patent_app_number] => 8/412505 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 144 [patent_figures_cnt] => 200 [patent_no_of_words] => 45550 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687387.pdf [firstpage_image] =>[orig_patent_app_number] => 412505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/412505
Enhanced active port replicator having expansion and upgrade capabilities Mar 23, 1995 Issued
Array ( [id] => 3700699 [patent_doc_number] => 05644730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Dual mode binary sensor for bus operation' [patent_app_type] => 1 [patent_app_number] => 8/409262 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2933 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644730.pdf [firstpage_image] =>[orig_patent_app_number] => 409262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/409262
Dual mode binary sensor for bus operation Mar 21, 1995 Issued
Array ( [id] => 3807533 [patent_doc_number] => 05842037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Interference reduction in TDM-communication/computing devices' [patent_app_type] => 1 [patent_app_number] => 8/406583 [patent_app_country] => US [patent_app_date] => 1995-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2006 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/842/05842037.pdf [firstpage_image] =>[orig_patent_app_number] => 406583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/406583
Interference reduction in TDM-communication/computing devices Mar 19, 1995 Issued
08/405520 SYMMETRIC MULTIPROCESSING SYSTEM WITH UNIFIED ENVIRONMENT AND DISTRIBUTED SYSTEM FUNCTIONS Mar 15, 1995 Abandoned
Array ( [id] => 3603579 [patent_doc_number] => 05586286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Memory controller having flip-flops for synchronously generating DRAM address and control signals from a single chip' [patent_app_type] => 1 [patent_app_number] => 8/404935 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 78 [patent_no_of_words] => 29598 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586286.pdf [firstpage_image] =>[orig_patent_app_number] => 404935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/404935
Memory controller having flip-flops for synchronously generating DRAM address and control signals from a single chip Mar 12, 1995 Issued
08/396488 READ STREAMING TECHNIQUE PROVIDING ENHANCED PERFORMANCE FOR COMMUNICATING SERIALIZED DATA READ FROM A MEMORY Mar 1, 1995 Abandoned
Array ( [id] => 4168525 [patent_doc_number] => 06149319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Computer system host adapter for controlling signal levels to peripheral cards' [patent_app_type] => 1 [patent_app_number] => 8/388615 [patent_app_country] => US [patent_app_date] => 1995-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 15596 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/149/06149319.pdf [firstpage_image] =>[orig_patent_app_number] => 388615 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/388615
Computer system host adapter for controlling signal levels to peripheral cards Feb 13, 1995 Issued
Array ( [id] => 3909647 [patent_doc_number] => 05835711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method and system for implementing multiple leaky bucket checkers using a hybrid synchronous/asynchronous update mechanism' [patent_app_type] => 1 [patent_app_number] => 8/382464 [patent_app_country] => US [patent_app_date] => 1995-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7145 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835711.pdf [firstpage_image] =>[orig_patent_app_number] => 382464 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/382464
Method and system for implementing multiple leaky bucket checkers using a hybrid synchronous/asynchronous update mechanism Jan 31, 1995 Issued
Array ( [id] => 3966745 [patent_doc_number] => 05999742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Dual latch data transfer pacing logic using a timer to maintain a data transfer interval' [patent_app_type] => 1 [patent_app_number] => 8/378660 [patent_app_country] => US [patent_app_date] => 1995-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 2 [patent_no_of_words] => 1245 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999742.pdf [firstpage_image] =>[orig_patent_app_number] => 378660 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/378660
Dual latch data transfer pacing logic using a timer to maintain a data transfer interval Jan 25, 1995 Issued
Array ( [id] => 3556280 [patent_doc_number] => 05555390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Data storage method and subsystem including a device controller for respecifying an amended start address' [patent_app_type] => 1 [patent_app_number] => 8/375064 [patent_app_country] => US [patent_app_date] => 1995-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10148 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555390.pdf [firstpage_image] =>[orig_patent_app_number] => 375064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375064
Data storage method and subsystem including a device controller for respecifying an amended start address Jan 18, 1995 Issued
Array ( [id] => 3636626 [patent_doc_number] => 05613162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method and apparatus for performing efficient direct memory access data transfers' [patent_app_type] => 1 [patent_app_number] => 8/368474 [patent_app_country] => US [patent_app_date] => 1995-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11705 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/613/05613162.pdf [firstpage_image] =>[orig_patent_app_number] => 368474 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/368474
Method and apparatus for performing efficient direct memory access data transfers Jan 3, 1995 Issued
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