| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05802389
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Expansion module address method and apparatus for a programmable logic controller'
[patent_app_type] => 1
[patent_app_number] => 8/365655
[patent_app_country] => US
[patent_app_date] => 1994-12-29
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[firstpage_image] =>[orig_patent_app_number] => 365655
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/365655 | Expansion module address method and apparatus for a programmable logic controller | Dec 28, 1994 | Issued |
Array
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[id] => 3901902
[patent_doc_number] => 05715475
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Topological identification and initialization of a system for processing video information'
[patent_app_type] => 1
[patent_app_number] => 8/366256
[patent_app_country] => US
[patent_app_date] => 1994-12-29
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[firstpage_image] =>[orig_patent_app_number] => 366256
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/366256 | Topological identification and initialization of a system for processing video information | Dec 28, 1994 | Issued |
| 08/365355 | METHOD AND APPARATUS FOR NETWORK INTERFACING WITH AUTOMATIC RECEIVER NODE AND TRANSMIT NODE SELECTION CAPABILTIY | Dec 27, 1994 | Abandoned |
| 08/360332 | METHOD AND APPARATUS FOR CACHE MEMORY REPLACEMENT LINE IDENTIFICATION | Dec 20, 1994 | Abandoned |
Array
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[id] => 3737001
[patent_doc_number] => 05701503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Method and apparatus for transferring information between a processor and a memory system'
[patent_app_type] => 1
[patent_app_number] => 8/360331
[patent_app_country] => US
[patent_app_date] => 1994-12-21
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[pdf_file] => patents/05/701/05701503.pdf
[firstpage_image] =>[orig_patent_app_number] => 360331
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/360331 | Method and apparatus for transferring information between a processor and a memory system | Dec 20, 1994 | Issued |
Array
(
[id] => 3530401
[patent_doc_number] => 05577224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Method and system for caching data'
[patent_app_type] => 1
[patent_app_number] => 8/356077
[patent_app_country] => US
[patent_app_date] => 1994-12-13
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[firstpage_image] =>[orig_patent_app_number] => 356077
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/356077 | Method and system for caching data | Dec 12, 1994 | Issued |
Array
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[patent_doc_number] => 05613076
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'System and method for providing uniform access to a SCSI bus by altering the arbitration phase associated with the SCSI bus'
[patent_app_type] => 1
[patent_app_number] => 8/352051
[patent_app_country] => US
[patent_app_date] => 1994-11-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/352051 | System and method for providing uniform access to a SCSI bus by altering the arbitration phase associated with the SCSI bus | Nov 29, 1994 | Issued |
Array
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[patent_doc_number] => 05724612
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[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Information transfer apparatus and information recording apparatus including transfer control means for determining a transfer sequence of plural information blocks'
[patent_app_type] => 1
[patent_app_number] => 8/346413
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/346413 | Information transfer apparatus and information recording apparatus including transfer control means for determining a transfer sequence of plural information blocks | Nov 28, 1994 | Issued |
Array
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[id] => 3636642
[patent_doc_number] => 05613163
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Method and system for predefined suspension and resumption control over I/O programs'
[patent_app_type] => 1
[patent_app_number] => 8/342459
[patent_app_country] => US
[patent_app_date] => 1994-11-18
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[pdf_file] => patents/05/613/05613163.pdf
[firstpage_image] =>[orig_patent_app_number] => 342459
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/342459 | Method and system for predefined suspension and resumption control over I/O programs | Nov 17, 1994 | Issued |
Array
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[id] => 3998489
[patent_doc_number] => 05862388
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Interrupt-time processing of received signals'
[patent_app_type] => 1
[patent_app_number] => 8/341398
[patent_app_country] => US
[patent_app_date] => 1994-11-16
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[patent_drawing_sheets_cnt] => 57
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[pdf_file] => patents/05/862/05862388.pdf
[firstpage_image] =>[orig_patent_app_number] => 341398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/341398 | Interrupt-time processing of received signals | Nov 15, 1994 | Issued |
Array
(
[id] => 3877574
[patent_doc_number] => 05796946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Multi-processor system barrier synchronizer not requiring repeated intializations of shared region'
[patent_app_type] => 1
[patent_app_number] => 8/339278
[patent_app_country] => US
[patent_app_date] => 1994-11-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/339278 | Multi-processor system barrier synchronizer not requiring repeated intializations of shared region | Nov 9, 1994 | Issued |
| 08/338732 | PRINT CONTROL APPARATUS FOR COMMUNICATING WITH A SELECTED EXTERNAL APPARATUS TO CONTROL A PRINTER | Nov 8, 1994 | Abandoned |
Array
(
[id] => 3761439
[patent_doc_number] => 05717948
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Interface circuit associated with a processor to exchange digital data in series with a peripheral device'
[patent_app_type] => 1
[patent_app_number] => 8/335472
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[patent_app_date] => 1994-11-07
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[pdf_file] => patents/05/717/05717948.pdf
[firstpage_image] =>[orig_patent_app_number] => 335472
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/335472 | Interface circuit associated with a processor to exchange digital data in series with a peripheral device | Nov 6, 1994 | Issued |
Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'I/O interface control method and data processing equipment which completes I/O operation in execution when abnormal state occurs'
[patent_app_type] => 1
[patent_app_number] => 8/330023
[patent_app_country] => US
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Array
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Array
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Array
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Array
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