Search

Ario Etienne

Supervisory Patent Examiner (ID: 13470, Phone: (571)272-4001 , Office: P/2457 )

Most Active Art Unit
2781
Art Unit(s)
2457, 2781, 2155, 2157, 2312, 2305, 2787
Total Applications
502
Issued Applications
404
Pending Applications
51
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3762740 [patent_doc_number] => 05802389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Expansion module address method and apparatus for a programmable logic controller' [patent_app_type] => 1 [patent_app_number] => 8/365655 [patent_app_country] => US [patent_app_date] => 1994-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 11388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802389.pdf [firstpage_image] =>[orig_patent_app_number] => 365655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/365655
Expansion module address method and apparatus for a programmable logic controller Dec 28, 1994 Issued
Array ( [id] => 3901902 [patent_doc_number] => 05715475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Topological identification and initialization of a system for processing video information' [patent_app_type] => 1 [patent_app_number] => 8/366256 [patent_app_country] => US [patent_app_date] => 1994-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4738 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715475.pdf [firstpage_image] =>[orig_patent_app_number] => 366256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/366256
Topological identification and initialization of a system for processing video information Dec 28, 1994 Issued
08/365355 METHOD AND APPARATUS FOR NETWORK INTERFACING WITH AUTOMATIC RECEIVER NODE AND TRANSMIT NODE SELECTION CAPABILTIY Dec 27, 1994 Abandoned
08/360332 METHOD AND APPARATUS FOR CACHE MEMORY REPLACEMENT LINE IDENTIFICATION Dec 20, 1994 Abandoned
Array ( [id] => 3737001 [patent_doc_number] => 05701503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method and apparatus for transferring information between a processor and a memory system' [patent_app_type] => 1 [patent_app_number] => 8/360331 [patent_app_country] => US [patent_app_date] => 1994-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11632 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701503.pdf [firstpage_image] =>[orig_patent_app_number] => 360331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/360331
Method and apparatus for transferring information between a processor and a memory system Dec 20, 1994 Issued
Array ( [id] => 3530401 [patent_doc_number] => 05577224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Method and system for caching data' [patent_app_type] => 1 [patent_app_number] => 8/356077 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4982 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577224.pdf [firstpage_image] =>[orig_patent_app_number] => 356077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/356077
Method and system for caching data Dec 12, 1994 Issued
Array ( [id] => 3635270 [patent_doc_number] => 05613076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'System and method for providing uniform access to a SCSI bus by altering the arbitration phase associated with the SCSI bus' [patent_app_type] => 1 [patent_app_number] => 8/352051 [patent_app_country] => US [patent_app_date] => 1994-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10530 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/613/05613076.pdf [firstpage_image] =>[orig_patent_app_number] => 352051 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/352051
System and method for providing uniform access to a SCSI bus by altering the arbitration phase associated with the SCSI bus Nov 29, 1994 Issued
Array ( [id] => 3903683 [patent_doc_number] => 05724612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Information transfer apparatus and information recording apparatus including transfer control means for determining a transfer sequence of plural information blocks' [patent_app_type] => 1 [patent_app_number] => 8/346413 [patent_app_country] => US [patent_app_date] => 1994-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 8473 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724612.pdf [firstpage_image] =>[orig_patent_app_number] => 346413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346413
Information transfer apparatus and information recording apparatus including transfer control means for determining a transfer sequence of plural information blocks Nov 28, 1994 Issued
Array ( [id] => 3636642 [patent_doc_number] => 05613163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method and system for predefined suspension and resumption control over I/O programs' [patent_app_type] => 1 [patent_app_number] => 8/342459 [patent_app_country] => US [patent_app_date] => 1994-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 11697 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/613/05613163.pdf [firstpage_image] =>[orig_patent_app_number] => 342459 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/342459
Method and system for predefined suspension and resumption control over I/O programs Nov 17, 1994 Issued
Array ( [id] => 3998489 [patent_doc_number] => 05862388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Interrupt-time processing of received signals' [patent_app_type] => 1 [patent_app_number] => 8/341398 [patent_app_country] => US [patent_app_date] => 1994-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 53770 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862388.pdf [firstpage_image] =>[orig_patent_app_number] => 341398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341398
Interrupt-time processing of received signals Nov 15, 1994 Issued
Array ( [id] => 3877574 [patent_doc_number] => 05796946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Multi-processor system barrier synchronizer not requiring repeated intializations of shared region' [patent_app_type] => 1 [patent_app_number] => 8/339278 [patent_app_country] => US [patent_app_date] => 1994-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4169 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796946.pdf [firstpage_image] =>[orig_patent_app_number] => 339278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339278
Multi-processor system barrier synchronizer not requiring repeated intializations of shared region Nov 9, 1994 Issued
08/338732 PRINT CONTROL APPARATUS FOR COMMUNICATING WITH A SELECTED EXTERNAL APPARATUS TO CONTROL A PRINTER Nov 8, 1994 Abandoned
Array ( [id] => 3761439 [patent_doc_number] => 05717948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Interface circuit associated with a processor to exchange digital data in series with a peripheral device' [patent_app_type] => 1 [patent_app_number] => 8/335472 [patent_app_country] => US [patent_app_date] => 1994-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5548 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717948.pdf [firstpage_image] =>[orig_patent_app_number] => 335472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335472
Interface circuit associated with a processor to exchange digital data in series with a peripheral device Nov 6, 1994 Issued
Array ( [id] => 3718144 [patent_doc_number] => 05655076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'I/O interface control method and data processing equipment which completes I/O operation in execution when abnormal state occurs' [patent_app_type] => 1 [patent_app_number] => 8/330023 [patent_app_country] => US [patent_app_date] => 1994-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4569 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/655/05655076.pdf [firstpage_image] =>[orig_patent_app_number] => 330023 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/330023
I/O interface control method and data processing equipment which completes I/O operation in execution when abnormal state occurs Oct 26, 1994 Issued
Array ( [id] => 3621741 [patent_doc_number] => 05590336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method and apparatus for performing overlapping service of multiple IDE peripheral devices' [patent_app_type] => 1 [patent_app_number] => 8/328481 [patent_app_country] => US [patent_app_date] => 1994-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7636 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590336.pdf [firstpage_image] =>[orig_patent_app_number] => 328481 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/328481
Method and apparatus for performing overlapping service of multiple IDE peripheral devices Oct 24, 1994 Issued
Array ( [id] => 3632654 [patent_doc_number] => 05642516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Selective shadowing of registers for interrupt processing' [patent_app_type] => 1 [patent_app_number] => 8/324077 [patent_app_country] => US [patent_app_date] => 1994-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2964 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642516.pdf [firstpage_image] =>[orig_patent_app_number] => 324077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/324077
Selective shadowing of registers for interrupt processing Oct 13, 1994 Issued
Array ( [id] => 3673195 [patent_doc_number] => 05649152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method and system for providing a static snapshot of data stored on a mass storage system' [patent_app_type] => 1 [patent_app_number] => 8/322697 [patent_app_country] => US [patent_app_date] => 1994-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4089 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649152.pdf [firstpage_image] =>[orig_patent_app_number] => 322697 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/322697
Method and system for providing a static snapshot of data stored on a mass storage system Oct 12, 1994 Issued
Array ( [id] => 3641894 [patent_doc_number] => 05687327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'System and method for allocating bus resources in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/317007 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2868 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687327.pdf [firstpage_image] =>[orig_patent_app_number] => 317007 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317007
System and method for allocating bus resources in a data processing system Oct 2, 1994 Issued
Array ( [id] => 4225607 [patent_doc_number] => 06029217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Queued arbitration mechanism for data processing system' [patent_app_type] => 1 [patent_app_number] => 8/317006 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3159 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029217.pdf [firstpage_image] =>[orig_patent_app_number] => 317006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317006
Queued arbitration mechanism for data processing system Oct 2, 1994 Issued
Array ( [id] => 3677624 [patent_doc_number] => 05668969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Address selective emulation routine pointer address mapping system' [patent_app_type] => 1 [patent_app_number] => 8/311880 [patent_app_country] => US [patent_app_date] => 1994-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8635 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668969.pdf [firstpage_image] =>[orig_patent_app_number] => 311880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/311880
Address selective emulation routine pointer address mapping system Sep 25, 1994 Issued
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