Search

Ario Etienne

Supervisory Patent Examiner (ID: 13470, Phone: (571)272-4001 , Office: P/2457 )

Most Active Art Unit
2781
Art Unit(s)
2457, 2781, 2155, 2157, 2312, 2305, 2787
Total Applications
502
Issued Applications
404
Pending Applications
51
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4280349 [patent_doc_number] => 06260087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Embedded configurable logic ASIC' [patent_app_type] => 1 [patent_app_number] => 9/261244 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4146 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260087.pdf [firstpage_image] =>[orig_patent_app_number] => 261244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261244
Embedded configurable logic ASIC Mar 2, 1999 Issued
Array ( [id] => 1434032 [patent_doc_number] => 06341322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method for interfacing two buses' [patent_app_type] => B1 [patent_app_number] => 09/258095 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9534 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341322.pdf [firstpage_image] =>[orig_patent_app_number] => 09258095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258095
Method for interfacing two buses Feb 24, 1999 Issued
Array ( [id] => 4207021 [patent_doc_number] => 06131166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'System and method for cross-platform application level power management' [patent_app_type] => 1 [patent_app_number] => 9/256826 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12169 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131166.pdf [firstpage_image] =>[orig_patent_app_number] => 256826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256826
System and method for cross-platform application level power management Feb 23, 1999 Issued
Array ( [id] => 4325097 [patent_doc_number] => 06253266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Apparatus and method for controlling information flow in a card cage having multiple backplanes' [patent_app_type] => 1 [patent_app_number] => 9/251898 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6300 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253266.pdf [firstpage_image] =>[orig_patent_app_number] => 251898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251898
Apparatus and method for controlling information flow in a card cage having multiple backplanes Feb 18, 1999 Issued
Array ( [id] => 4326067 [patent_doc_number] => 06253330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Redundant regulated power supply system with monitoring of the backup power supply' [patent_app_type] => 1 [patent_app_number] => 9/251842 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1915 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253330.pdf [firstpage_image] =>[orig_patent_app_number] => 251842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251842
Redundant regulated power supply system with monitoring of the backup power supply Feb 16, 1999 Issued
Array ( [id] => 4403772 [patent_doc_number] => 06263393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Bus switch for realizing bus transactions across two or more buses' [patent_app_type] => 1 [patent_app_number] => 9/251434 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 41 [patent_no_of_words] => 20750 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263393.pdf [firstpage_image] =>[orig_patent_app_number] => 251434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251434
Bus switch for realizing bus transactions across two or more buses Feb 16, 1999 Issued
Array ( [id] => 4279624 [patent_doc_number] => 06205508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for distributing interrupts in a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 9/251265 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 14693 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205508.pdf [firstpage_image] =>[orig_patent_app_number] => 251265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251265
Method for distributing interrupts in a multi-processor system Feb 15, 1999 Issued
Array ( [id] => 4304554 [patent_doc_number] => 06269416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Adaptive PCI slot' [patent_app_type] => 1 [patent_app_number] => 9/245509 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8030 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269416.pdf [firstpage_image] =>[orig_patent_app_number] => 245509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245509
Adaptive PCI slot Feb 1, 1999 Issued
Array ( [id] => 4318488 [patent_doc_number] => 06182232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Power and thermal management based on a power supply output' [patent_app_type] => 1 [patent_app_number] => 9/239635 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2617 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182232.pdf [firstpage_image] =>[orig_patent_app_number] => 239635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239635
Power and thermal management based on a power supply output Jan 28, 1999 Issued
Array ( [id] => 4279580 [patent_doc_number] => 06205505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for reducing electromagnetic interference (EMI) in a universal serial bus transmission system' [patent_app_type] => 1 [patent_app_number] => 9/237184 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1790 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205505.pdf [firstpage_image] =>[orig_patent_app_number] => 237184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237184
Method for reducing electromagnetic interference (EMI) in a universal serial bus transmission system Jan 24, 1999 Issued
Array ( [id] => 4178979 [patent_doc_number] => 06115779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Interrupt management system having batch mechanism for handling interrupt events' [patent_app_type] => 1 [patent_app_number] => 9/234456 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4531 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115779.pdf [firstpage_image] =>[orig_patent_app_number] => 234456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/234456
Interrupt management system having batch mechanism for handling interrupt events Jan 20, 1999 Issued
Array ( [id] => 4118094 [patent_doc_number] => 06098141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Compact ISA-bus interface' [patent_app_type] => 1 [patent_app_number] => 9/233230 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7330 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098141.pdf [firstpage_image] =>[orig_patent_app_number] => 233230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233230
Compact ISA-bus interface Jan 18, 1999 Issued
Array ( [id] => 1602106 [patent_doc_number] => 06493755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Automatic notification rule definition for a network management system' [patent_app_type] => B1 [patent_app_number] => 09/231251 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4890 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493755.pdf [firstpage_image] =>[orig_patent_app_number] => 09231251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231251
Automatic notification rule definition for a network management system Jan 14, 1999 Issued
Array ( [id] => 1538934 [patent_doc_number] => 06412007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Mechanism for authorizing a data communication session between a client and a server' [patent_app_type] => B1 [patent_app_number] => 09/231926 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 15277 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412007.pdf [firstpage_image] =>[orig_patent_app_number] => 09231926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231926
Mechanism for authorizing a data communication session between a client and a server Jan 13, 1999 Issued
Array ( [id] => 4352259 [patent_doc_number] => 06314522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Multi-voltage level CPU module' [patent_app_type] => 1 [patent_app_number] => 9/229483 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5533 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314522.pdf [firstpage_image] =>[orig_patent_app_number] => 229483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229483
Multi-voltage level CPU module Jan 12, 1999 Issued
Array ( [id] => 4294571 [patent_doc_number] => 06324615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 9/229035 [patent_app_country] => US [patent_app_date] => 1999-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2859 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324615.pdf [firstpage_image] =>[orig_patent_app_number] => 229035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229035
Data processor Jan 11, 1999 Issued
Array ( [id] => 4392368 [patent_doc_number] => 06289465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'System and method for power optimization in parallel units' [patent_app_type] => 1 [patent_app_number] => 9/228884 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6001 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289465.pdf [firstpage_image] =>[orig_patent_app_number] => 228884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/228884
System and method for power optimization in parallel units Jan 10, 1999 Issued
Array ( [id] => 4381077 [patent_doc_number] => 06256698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of and apparatus for providing self-sustained even arbitration within an IEEE 1394 serial bus network of devices' [patent_app_type] => 1 [patent_app_number] => 9/227951 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5570 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256698.pdf [firstpage_image] =>[orig_patent_app_number] => 227951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227951
Method of and apparatus for providing self-sustained even arbitration within an IEEE 1394 serial bus network of devices Jan 10, 1999 Issued
Array ( [id] => 4280517 [patent_doc_number] => 06260096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Read latency across a bridge' [patent_app_type] => 1 [patent_app_number] => 9/227995 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3119 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260096.pdf [firstpage_image] =>[orig_patent_app_number] => 227995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227995
Read latency across a bridge Jan 7, 1999 Issued
Array ( [id] => 4203531 [patent_doc_number] => 06161161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'System and method for coupling a local bus to a peripheral component interconnect (PCI) bus' [patent_app_type] => 1 [patent_app_number] => 9/227634 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4205 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161161.pdf [firstpage_image] =>[orig_patent_app_number] => 227634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227634
System and method for coupling a local bus to a peripheral component interconnect (PCI) bus Jan 7, 1999 Issued
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