Search

Arman Milanian

Examiner (ID: 4027, Phone: (571)272-9846 , Office: P/3723 )

Most Active Art Unit
3723
Art Unit(s)
3723
Total Applications
392
Issued Applications
225
Pending Applications
0
Abandoned Applications
167

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19755843 [patent_doc_number] => 20250044408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => Vehicle Radar Sensor Utilizing Non-Uniform Frequency Modulated Continuous Wave (FMCW) Chirps [patent_app_type] => utility [patent_app_number] => 18/767794 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767794
Vehicle Radar Sensor Utilizing Non-Uniform Frequency Modulated Continuous Wave (FMCW) Chirps Jul 8, 2024 Pending
Array ( [id] => 19687696 [patent_doc_number] => 20250006241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => TECHNIQUES TO REFRESH MEMORY SYSTEMS OPERATING IN LOW POWER STATES BASED ON TEMPERATURE [patent_app_type] => utility [patent_app_number] => 18/759484 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759484
TECHNIQUES TO REFRESH MEMORY SYSTEMS OPERATING IN LOW POWER STATES BASED ON TEMPERATURE Jun 27, 2024 Pending
Array ( [id] => 19749212 [patent_doc_number] => 20250037777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY DEVICE CAPABLE OF CHANGING PASS VOLTAGE, MEMORY SYSTEM, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/753133 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753133 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753133
MEMORY DEVICE CAPABLE OF CHANGING PASS VOLTAGE, MEMORY SYSTEM, AND OPERATING METHOD OF THE MEMORY DEVICE Jun 24, 2024 Pending
Array ( [id] => 20002081 [patent_doc_number] => 20250140303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR DEVICE PERFORMING REPLICA ROUTING [patent_app_type] => utility [patent_app_number] => 18/751894 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751894 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751894
SEMICONDUCTOR DEVICE PERFORMING REPLICA ROUTING Jun 23, 2024 Pending
Array ( [id] => 19661801 [patent_doc_number] => 20240428866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/749384 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749384 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749384
SEMICONDUCTOR MEMORY DEVICE Jun 19, 2024 Pending
Array ( [id] => 20429390 [patent_doc_number] => 20250391483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => PROGRAMMING WITHOUT PRE-CHARGE IN NONVOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/748836 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748836
PROGRAMMING WITHOUT PRE-CHARGE IN NONVOLATILE MEMORY DEVICES Jun 19, 2024 Pending
Array ( [id] => 19661805 [patent_doc_number] => 20240428870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND DATA ERASING METHOD [patent_app_type] => utility [patent_app_number] => 18/744919 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744919
SEMICONDUCTOR MEMORY DEVICE AND DATA ERASING METHOD Jun 16, 2024 Pending
Array ( [id] => 19618910 [patent_doc_number] => 20240404590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/742753 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742753
TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING Jun 12, 2024 Pending
Array ( [id] => 19712386 [patent_doc_number] => 20250022528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => HEAT GENERATION CONTROL FOR MEMORY SYSTEM EVALUATION [patent_app_type] => utility [patent_app_number] => 18/742097 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742097 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742097
HEAT GENERATION CONTROL FOR MEMORY SYSTEM EVALUATION Jun 12, 2024 Pending
Array ( [id] => 20422834 [patent_doc_number] => 20250384919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/741248 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741248
SEMICONDUCTOR DEVICE Jun 11, 2024 Pending
Array ( [id] => 20530171 [patent_doc_number] => 12548612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Semiconductor memory device with spin-orbit coupling channel [patent_app_type] => utility [patent_app_number] => 18/662053 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 1216 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662053 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662053
Semiconductor memory device with spin-orbit coupling channel May 12, 2024 Issued
Array ( [id] => 20352500 [patent_doc_number] => 20250349352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => FOUR-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL WITH ENHANCED DATA RETENTION [patent_app_type] => utility [patent_app_number] => 18/661126 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661126
Four-transistor static random access memory cell with enhanced data retention May 9, 2024 Issued
Array ( [id] => 20352507 [patent_doc_number] => 20250349359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => PRECHARGING METHOD AND PROGRAMMING METHOD FOR 3D MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/658997 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658997
PRECHARGING METHOD AND PROGRAMMING METHOD FOR 3D MEMORY DEVICE May 8, 2024 Pending
Array ( [id] => 20139197 [patent_doc_number] => 20250246241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => METHOD OF OPTIMIZING PASS VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/657789 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657789
METHOD OF OPTIMIZING PASS VOLTAGE May 7, 2024 Pending
Array ( [id] => 20010873 [patent_doc_number] => 20250149095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/657248 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657248
MEMORY DEVICE AND METHOD OF OPERATING THE SAME May 6, 2024 Pending
Array ( [id] => 20140973 [patent_doc_number] => 20250248017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => SRAM CELL STRUCTURE WITH 3 P-CHANNEL TRANSISTORS AND 3 N-CHANNEL TRANSISTORS AND METHOD OF OPERATING THE SRAM CELL [patent_app_type] => utility [patent_app_number] => 18/625310 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625310
Sram cell structure with 3 p-channel transistors and 3 n-channel transistors and method of operating the sram cell Apr 2, 2024 Issued
Array ( [id] => 20283354 [patent_doc_number] => 20250308596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => TECHNIQUES FOR FASTER RAMP-UP TIMES FOR UNSELECTED WORD LINES IN NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/617898 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617898
TECHNIQUES FOR FASTER RAMP-UP TIMES FOR UNSELECTED WORD LINES IN NON-VOLATILE MEMORY Mar 26, 2024 Pending
Array ( [id] => 19483735 [patent_doc_number] => 20240331777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CASCADE MODEL FOR DETERMINING READ LEVEL VOLTAGE OFFSETS [patent_app_type] => utility [patent_app_number] => 18/615051 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615051 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615051
CASCADE MODEL FOR DETERMINING READ LEVEL VOLTAGE OFFSETS Mar 24, 2024 Pending
Array ( [id] => 19348901 [patent_doc_number] => 20240257865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MEMORY DEVICE AND METHOD FOR COMPUTING-IN-MEMORY (CIM) [patent_app_type] => utility [patent_app_number] => 18/608147 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608147
Memory device and method for computing-in- memory (CIM) Mar 17, 2024 Issued
Array ( [id] => 19452399 [patent_doc_number] => 20240312529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => CORRECTIVE READ WITH PARTIAL BLOCK OFFSET IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/602960 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602960
CORRECTIVE READ WITH PARTIAL BLOCK OFFSET IN A MEMORY DEVICE Mar 11, 2024 Pending
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