Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8820079 [patent_doc_number] => 20130121124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'VERIFYING DEVICE, IMAGING DEVICE HAVING VERIFYING FUNCTION, AND VERIFYING METHOD' [patent_app_type] => utility [patent_app_number] => 13/673053 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9376 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673053
Verifying device, imaging device having verifying function, and verifying method Nov 8, 2012 Issued
Array ( [id] => 9479449 [patent_doc_number] => 20140136912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'COMBO DYNAMIC FLOP WITH SCAN' [patent_app_type] => utility [patent_app_number] => 13/673503 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4910 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673503 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673503
Combo dynamic flop with scan Nov 8, 2012 Issued
Array ( [id] => 9765942 [patent_doc_number] => 08850290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Error rate threshold for storage of data' [patent_app_type] => utility [patent_app_number] => 13/673657 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673657
Error rate threshold for storage of data Nov 8, 2012 Issued
Array ( [id] => 10879458 [patent_doc_number] => 08904256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'Method and apparatus for low-pin count testing of integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/673522 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 11053 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673522 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673522
Method and apparatus for low-pin count testing of integrated circuits Nov 8, 2012 Issued
Array ( [id] => 9961353 [patent_doc_number] => 09009578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-14 [patent_title] => 'Methodology for improved bit-flipping decoder in 1-read and 2-read scenarios' [patent_app_type] => utility [patent_app_number] => 13/673371 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 12112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673371 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673371
Methodology for improved bit-flipping decoder in 1-read and 2-read scenarios Nov 8, 2012 Issued
Array ( [id] => 9479446 [patent_doc_number] => 20140136909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'TESTING OF SRAMS' [patent_app_type] => utility [patent_app_number] => 13/672799 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672799 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672799
Testing of SRAMS Nov 8, 2012 Issued
Array ( [id] => 9886033 [patent_doc_number] => 08972818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Algorithm for optimal usage of external memory tuning sequence' [patent_app_type] => utility [patent_app_number] => 13/672693 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672693 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672693
Algorithm for optimal usage of external memory tuning sequence Nov 7, 2012 Issued
Array ( [id] => 8816586 [patent_doc_number] => 20130117631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'ERROR DETECTION AND CORRECTION FOR EXTERNAL DRAM' [patent_app_type] => utility [patent_app_number] => 13/660737 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660737 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/660737
Error detection and correction for external DRAM Oct 24, 2012 Issued
Array ( [id] => 8661339 [patent_doc_number] => 20130042168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'CHECKSUM CALCULATION, PREDICTION AND VALIDATION' [patent_app_type] => utility [patent_app_number] => 13/653761 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5457 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653761 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653761
Checksum calculation, prediction and validation Oct 16, 2012 Issued
Array ( [id] => 11769422 [patent_doc_number] => 09378086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Methods and apparatus for improved DMX512 communication' [patent_app_type] => utility [patent_app_number] => 14/350420 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7801 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14350420 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/350420
Methods and apparatus for improved DMX512 communication Oct 7, 2012 Issued
Array ( [id] => 8861559 [patent_doc_number] => 08464113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-11 [patent_title] => 'Scan architecture for full custom blocks with improved scan latch' [patent_app_type] => utility [patent_app_number] => 13/617586 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13617586 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/617586
Scan architecture for full custom blocks with improved scan latch Sep 13, 2012 Issued
Array ( [id] => 10895052 [patent_doc_number] => 08918683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'One-time program cell array circuit and memory device including the same' [patent_app_type] => utility [patent_app_number] => 13/619115 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4759 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619115 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619115
One-time program cell array circuit and memory device including the same Sep 13, 2012 Issued
Array ( [id] => 9062917 [patent_doc_number] => 08549371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/613652 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4137 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13613652 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/613652
Semiconductor memory device Sep 12, 2012 Issued
Array ( [id] => 9012520 [patent_doc_number] => 08527841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Apparatus, system, and method for using multi-level cell solid-state storage as reduced-level cell solid-state storage' [patent_app_type] => utility [patent_app_number] => 13/609527 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 8143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609527
Apparatus, system, and method for using multi-level cell solid-state storage as reduced-level cell solid-state storage Sep 10, 2012 Issued
Array ( [id] => 9297898 [patent_doc_number] => RE044764 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2014-02-11 [patent_title] => 'Serially decoded digital device testing' [patent_app_type] => reissue [patent_app_number] => 13/608701 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5785 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13608701 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/608701
Serially decoded digital device testing Sep 9, 2012 Issued
Array ( [id] => 9665911 [patent_doc_number] => 08812920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Test mode signal generation circuit' [patent_app_type] => utility [patent_app_number] => 13/604351 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4053 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604351
Test mode signal generation circuit Sep 4, 2012 Issued
Array ( [id] => 8935715 [patent_doc_number] => 08495437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/602906 [patent_app_country] => US [patent_app_date] => 2012-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 13476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602906
Semiconductor memory device Sep 3, 2012 Issued
Array ( [id] => 9527593 [patent_doc_number] => 08751885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Repair control circuit and semiconductor integrated circuit using the same' [patent_app_type] => utility [patent_app_number] => 13/602244 [patent_app_country] => US [patent_app_date] => 2012-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2510 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602244
Repair control circuit and semiconductor integrated circuit using the same Sep 2, 2012 Issued
Array ( [id] => 9507142 [patent_doc_number] => 08745472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Memory with segmented error correction codes' [patent_app_type] => utility [patent_app_number] => 13/602116 [patent_app_country] => US [patent_app_date] => 2012-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602116 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602116
Memory with segmented error correction codes Aug 31, 2012 Issued
Array ( [id] => 9829421 [patent_doc_number] => 08938658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Statistical read comparison signal generation for memory systems' [patent_app_type] => utility [patent_app_number] => 13/602031 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 16539 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602031 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602031
Statistical read comparison signal generation for memory systems Aug 30, 2012 Issued
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