Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9444270 [patent_doc_number] => 08713406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Erasing a non-volatile memory (NVM) system having error correction code (ECC)' [patent_app_type] => utility [patent_app_number] => 13/459344 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459344 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/459344
Erasing a non-volatile memory (NVM) system having error correction code (ECC) Apr 29, 2012 Issued
Array ( [id] => 9123884 [patent_doc_number] => 20130290806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'Systems and Methods for Data Decoder State Preservation During Extended Delay Processing' [patent_app_type] => utility [patent_app_number] => 13/459282 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/459282
Systems and methods for data decoder state preservation during extended delay processing Apr 29, 2012 Issued
Array ( [id] => 9123880 [patent_doc_number] => 20130290802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'VARIABLE ACKNOWLEDGE RATE TO REDUCE BUS CONTENTION IN PRESENCE OF COMMUNICATION ERRORS' [patent_app_type] => utility [patent_app_number] => 13/458522 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6047 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458522 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458522
Variable acknowledge rate to reduce bus contention in presence of communication errors Apr 26, 2012 Issued
Array ( [id] => 8580955 [patent_doc_number] => 08347187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Adaptive systems and methods for storing and retrieving data to and from memory cells' [patent_app_type] => utility [patent_app_number] => 13/459013 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459013 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/459013
Adaptive systems and methods for storing and retrieving data to and from memory cells Apr 26, 2012 Issued
Array ( [id] => 9404809 [patent_doc_number] => 08694873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Memory system and error correction method' [patent_app_type] => utility [patent_app_number] => 13/456567 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/456567
Memory system and error correction method Apr 25, 2012 Issued
Array ( [id] => 8485167 [patent_doc_number] => 20120284574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Non-Volatile Memory and Method Having Efficient On-Chip Block-Copying with Controlled Error Rate' [patent_app_type] => utility [patent_app_number] => 13/457247 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13457247 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/457247
Non-volatile memory and method having efficient on-chip block-copying with controlled error rate Apr 25, 2012 Issued
Array ( [id] => 9123883 [patent_doc_number] => 20130290805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'Distributed System for Fault-Tolerant Data Storage' [patent_app_type] => utility [patent_app_number] => 13/456102 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/456102
Distributed system for fault-tolerant data storage Apr 24, 2012 Issued
Array ( [id] => 9123883 [patent_doc_number] => 20130290805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'Distributed System for Fault-Tolerant Data Storage' [patent_app_type] => utility [patent_app_number] => 13/456102 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/456102
Distributed system for fault-tolerant data storage Apr 24, 2012 Issued
Array ( [id] => 8466946 [patent_doc_number] => 20120272114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'MEMORY CONTROLLER, MEMORY SYSTEM, AND OPERATING METHOD' [patent_app_type] => utility [patent_app_number] => 13/454301 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7552 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/454301
Memory controller, memory system, and operating method Apr 23, 2012 Issued
Array ( [id] => 9218501 [patent_doc_number] => 08631311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-14 [patent_title] => 'Data recovery using existing reconfigurable read channel hardware' [patent_app_type] => utility [patent_app_number] => 13/453729 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453729 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/453729
Data recovery using existing reconfigurable read channel hardware Apr 22, 2012 Issued
Array ( [id] => 8678771 [patent_doc_number] => 08386906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Multi-CSI (cyclic shifted identity) sub-matrix based LDPC (low density parity check) codes' [patent_app_type] => utility [patent_app_number] => 13/424159 [patent_app_country] => US [patent_app_date] => 2012-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 9245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/424159
Multi-CSI (cyclic shifted identity) sub-matrix based LDPC (low density parity check) codes Mar 18, 2012 Issued
Array ( [id] => 10053274 [patent_doc_number] => 09093154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Method, memory controller and system for reading data stored in flash memory' [patent_app_type] => utility [patent_app_number] => 13/351143 [patent_app_country] => US [patent_app_date] => 2012-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8787 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13351143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/351143
Method, memory controller and system for reading data stored in flash memory Jan 15, 2012 Issued
Array ( [id] => 8893788 [patent_doc_number] => 20130166972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Apparatus and Methods of Programming Memory Cells using Adjustable Charge State Level(s)' [patent_app_type] => utility [patent_app_number] => 13/335291 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6008 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335291 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335291
Apparatus and methods of programming memory cells using adjustable charge state level(s) Dec 21, 2011 Issued
Array ( [id] => 8868210 [patent_doc_number] => 20130151913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'Expedited Memory Drive Self Test' [patent_app_type] => utility [patent_app_number] => 13/323991 [patent_app_country] => US [patent_app_date] => 2011-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323991 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/323991
Expedited memory drive self test Dec 12, 2011 Issued
Array ( [id] => 10895061 [patent_doc_number] => 08918692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'Data throughput for cell-edge users in a LTE network using down-link repeaters and up link HARQ relays' [patent_app_type] => utility [patent_app_number] => 13/324599 [patent_app_country] => US [patent_app_date] => 2011-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 10507 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13324599 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/324599
Data throughput for cell-edge users in a LTE network using down-link repeaters and up link HARQ relays Dec 12, 2011 Issued
Array ( [id] => 9392467 [patent_doc_number] => 08689090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Apparatus and method for channel encoding and decoding based on low-density parity check code in multiple antenna communication system' [patent_app_type] => utility [patent_app_number] => 13/324517 [patent_app_country] => US [patent_app_date] => 2011-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9386 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13324517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/324517
Apparatus and method for channel encoding and decoding based on low-density parity check code in multiple antenna communication system Dec 12, 2011 Issued
Array ( [id] => 9458637 [patent_doc_number] => 08719663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Cross-decoding for non-volatile storage' [patent_app_type] => utility [patent_app_number] => 13/323769 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 11270 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323769 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/323769
Cross-decoding for non-volatile storage Dec 11, 2011 Issued
Array ( [id] => 8130675 [patent_doc_number] => 20120089888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'Systems and Methods for Multi-Level Quasi-Cyclic Low Density Parity Check Codes' [patent_app_type] => utility [patent_app_number] => 13/316858 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10077 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20120089888.pdf [firstpage_image] =>[orig_patent_app_number] => 13316858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316858
Systems and methods for multi-level quasi-cyclic low density parity check codes Dec 11, 2011 Issued
Array ( [id] => 9218490 [patent_doc_number] => 08631300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Systems and methods for scalable data processing shut down' [patent_app_type] => utility [patent_app_number] => 13/316741 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316741 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316741
Systems and methods for scalable data processing shut down Dec 11, 2011 Issued
Array ( [id] => 9187162 [patent_doc_number] => 08627162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Iimplementing enhanced aperture function calibration for logic built in self test (LBIST)' [patent_app_type] => utility [patent_app_number] => 13/316620 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316620 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316620
Iimplementing enhanced aperture function calibration for logic built in self test (LBIST) Dec 11, 2011 Issued
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