Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 146814 [patent_doc_number] => 07689930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Navigation of an N-dimensional hierarchical structure using a 2-dimensional controller' [patent_app_type] => utility [patent_app_number] => 12/406396 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2363 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689930.pdf [firstpage_image] =>[orig_patent_app_number] => 12406396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/406396
Navigation of an N-dimensional hierarchical structure using a 2-dimensional controller Mar 17, 2009 Issued
Array ( [id] => 5387502 [patent_doc_number] => 20090228747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Test system for conducting Parallel bit test' [patent_app_type] => utility [patent_app_number] => 12/382026 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228747.pdf [firstpage_image] =>[orig_patent_app_number] => 12382026 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/382026
Test system for conducting parallel bit test Mar 5, 2009 Issued
Array ( [id] => 5475977 [patent_doc_number] => 20090249143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'SCAN CONTROL METHOD, SCAN CONTROL CIRCUIT AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/396818 [patent_app_country] => US [patent_app_date] => 2009-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6330 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20090249143.pdf [firstpage_image] =>[orig_patent_app_number] => 12396818 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/396818
Scan control method, scan control circuit and apparatus Mar 2, 2009 Issued
Array ( [id] => 5387507 [patent_doc_number] => 20090228752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/396745 [patent_app_country] => US [patent_app_date] => 2009-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11359 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228752.pdf [firstpage_image] =>[orig_patent_app_number] => 12396745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/396745
Semiconductor integrated circuit Mar 2, 2009 Issued
Array ( [id] => 4443580 [patent_doc_number] => 07900114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Error detection in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/395490 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5388 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900114.pdf [firstpage_image] =>[orig_patent_app_number] => 12395490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/395490
Error detection in an integrated circuit Feb 26, 2009 Issued
Array ( [id] => 5526031 [patent_doc_number] => 20090196108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE TEST METHOD' [patent_app_type] => utility [patent_app_number] => 12/393145 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5601 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20090196108.pdf [firstpage_image] =>[orig_patent_app_number] => 12393145 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/393145
Semiconductor memory device and semiconductor memory device test method Feb 25, 2009 Issued
Array ( [id] => 4550159 [patent_doc_number] => 07925950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic' [patent_app_type] => utility [patent_app_number] => 12/393156 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/925/07925950.pdf [firstpage_image] =>[orig_patent_app_number] => 12393156 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/393156
Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic Feb 25, 2009 Issued
Array ( [id] => 6533828 [patent_doc_number] => 20100218054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Secure Scan Design' [patent_app_type] => utility [patent_app_number] => 12/391085 [patent_app_country] => US [patent_app_date] => 2009-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3229 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20100218054.pdf [firstpage_image] =>[orig_patent_app_number] => 12391085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/391085
Secure scan design Feb 22, 2009 Issued
Array ( [id] => 4447590 [patent_doc_number] => 07930602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Method and system for performing a double pass NTH fail bitmap of a device memory' [patent_app_type] => utility [patent_app_number] => 12/389748 [patent_app_country] => US [patent_app_date] => 2009-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930602.pdf [firstpage_image] =>[orig_patent_app_number] => 12389748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/389748
Method and system for performing a double pass NTH fail bitmap of a device memory Feb 19, 2009 Issued
Array ( [id] => 5548229 [patent_doc_number] => 20090158106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Position Independent Testing of Circuits' [patent_app_type] => utility [patent_app_number] => 12/389513 [patent_app_country] => US [patent_app_date] => 2009-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 27223 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158106.pdf [firstpage_image] =>[orig_patent_app_number] => 12389513 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/389513
Position independent testing of circuits Feb 19, 2009 Issued
Array ( [id] => 5459743 [patent_doc_number] => 20090259895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE PARALLEL BIT TEST CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/389607 [patent_app_country] => US [patent_app_date] => 2009-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8917 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20090259895.pdf [firstpage_image] =>[orig_patent_app_number] => 12389607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/389607
Semiconductor memory device parallel bit test circuits Feb 19, 2009 Issued
Array ( [id] => 7510597 [patent_doc_number] => 08037384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/340549 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7887 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037384.pdf [firstpage_image] =>[orig_patent_app_number] => 12340549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/340549
Semiconductor device Dec 18, 2008 Issued
Array ( [id] => 4441247 [patent_doc_number] => 07971120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Method and apparatus for covering a multilayer process space during at-speed testing' [patent_app_type] => utility [patent_app_number] => 12/340072 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4594 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971120.pdf [firstpage_image] =>[orig_patent_app_number] => 12340072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/340072
Method and apparatus for covering a multilayer process space during at-speed testing Dec 18, 2008 Issued
Array ( [id] => 5408773 [patent_doc_number] => 20090122671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Method and apparatus for recording data on and reproducing data from a recording medium and the recording medium' [patent_app_type] => utility [patent_app_number] => 12/314736 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5470 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20090122671.pdf [firstpage_image] =>[orig_patent_app_number] => 12314736 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/314736
Method and apparatus for recording data on and reproducing data from a recording medium and the recording medium Dec 15, 2008 Issued
Array ( [id] => 7521081 [patent_doc_number] => 07975190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'System and method for network device configuration' [patent_app_type] => utility [patent_app_number] => 12/336433 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975190.pdf [firstpage_image] =>[orig_patent_app_number] => 12336433 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/336433
System and method for network device configuration Dec 15, 2008 Issued
Array ( [id] => 4488717 [patent_doc_number] => 07908536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/329030 [patent_app_country] => US [patent_app_date] => 2008-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8799 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908536.pdf [firstpage_image] =>[orig_patent_app_number] => 12329030 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/329030
Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device Dec 4, 2008 Issued
Array ( [id] => 5381463 [patent_doc_number] => 20090193302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'SEMICONDUCRTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/272173 [patent_app_country] => US [patent_app_date] => 2008-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8797 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193302.pdf [firstpage_image] =>[orig_patent_app_number] => 12272173 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/272173
Semiconductor device Nov 16, 2008 Issued
Array ( [id] => 7521080 [patent_doc_number] => 07975189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Error rate estimation/application to code-rate adaption' [patent_app_type] => utility [patent_app_number] => 12/271050 [patent_app_country] => US [patent_app_date] => 2008-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10371 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975189.pdf [firstpage_image] =>[orig_patent_app_number] => 12271050 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/271050
Error rate estimation/application to code-rate adaption Nov 13, 2008 Issued
Array ( [id] => 7532637 [patent_doc_number] => 07844871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Test interface for memory elements' [patent_app_type] => utility [patent_app_number] => 12/268903 [patent_app_country] => US [patent_app_date] => 2008-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2714 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844871.pdf [firstpage_image] =>[orig_patent_app_number] => 12268903 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/268903
Test interface for memory elements Nov 10, 2008 Issued
Array ( [id] => 5437902 [patent_doc_number] => 20090172489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'CIRCUIT ARRANGEMENT AND METHOD FOR CHECKING THE FUNCTION OF A LOGIC CIRCUIT IN A CIRCUIT ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 12/268226 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7445 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172489.pdf [firstpage_image] =>[orig_patent_app_number] => 12268226 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/268226
Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement Nov 9, 2008 Issued
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