Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7993263 [patent_doc_number] => 08078940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/877287 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 9449 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078940.pdf [firstpage_image] =>[orig_patent_app_number] => 11877287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877287
Non-volatile semiconductor memory device Oct 22, 2007 Issued
Array ( [id] => 4966873 [patent_doc_number] => 20080109693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'HARQ TRANSMISSION FEEDBACK FOR HIGHER LAYER PROTOCOLS IN A COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/876811 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4068 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109693.pdf [firstpage_image] =>[orig_patent_app_number] => 11876811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/876811
HARQ transmission feedback for higher layer protocols in a communication system Oct 22, 2007 Issued
Array ( [id] => 258201 [patent_doc_number] => 07577889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-18 [patent_title] => 'Method for detecting software errors and vulnerabilities' [patent_app_type] => utility [patent_app_number] => 11/873125 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3132 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577889.pdf [firstpage_image] =>[orig_patent_app_number] => 11873125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873125
Method for detecting software errors and vulnerabilities Oct 15, 2007 Issued
Array ( [id] => 6617228 [patent_doc_number] => 20100293425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'PARAMETRIC SCAN REGISTER, DIGITAL CIRCUIT AND METHOD FOR TESTING A DIGITAL CIRCUIT USING SUCH REGISTER' [patent_app_type] => utility [patent_app_number] => 12/444443 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6530 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20100293425.pdf [firstpage_image] =>[orig_patent_app_number] => 12444443 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/444443
PARAMETRIC SCAN REGISTER, DIGITAL CIRCUIT AND METHOD FOR TESTING A DIGITAL CIRCUIT USING SUCH REGISTER Oct 4, 2007 Abandoned
Array ( [id] => 8158377 [patent_doc_number] => 08171380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Adaptive systems and methods for storing and retrieving data to and from memory cells' [patent_app_type] => utility [patent_app_number] => 11/867858 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5501 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171380.pdf [firstpage_image] =>[orig_patent_app_number] => 11867858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867858
Adaptive systems and methods for storing and retrieving data to and from memory cells Oct 4, 2007 Issued
Array ( [id] => 7495175 [patent_doc_number] => 08032812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-04 [patent_title] => 'Error correction decoding methods and apparatus' [patent_app_type] => utility [patent_app_number] => 11/867356 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2560 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032812.pdf [firstpage_image] =>[orig_patent_app_number] => 11867356 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867356
Error correction decoding methods and apparatus Oct 3, 2007 Issued
Array ( [id] => 7756633 [patent_doc_number] => 08112693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Error control code apparatuses and methods of using the same' [patent_app_type] => utility [patent_app_number] => 11/905734 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6166 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112693.pdf [firstpage_image] =>[orig_patent_app_number] => 11905734 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905734
Error control code apparatuses and methods of using the same Oct 2, 2007 Issued
Array ( [id] => 6568407 [patent_doc_number] => 20100046547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'METHOD AND APPARATUS FOR FRAME CONTROL HEADER DECODING' [patent_app_type] => utility [patent_app_number] => 11/858471 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046547.pdf [firstpage_image] =>[orig_patent_app_number] => 11858471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858471
Method and apparatus for frame control header decoding using cyclic shifting of bits Sep 19, 2007 Issued
Array ( [id] => 7595722 [patent_doc_number] => 07620860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'System and method of dynamically mapping out faulty memory areas' [patent_app_type] => utility [patent_app_number] => 11/851683 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620860.pdf [firstpage_image] =>[orig_patent_app_number] => 11851683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851683
System and method of dynamically mapping out faulty memory areas Sep 6, 2007 Issued
Array ( [id] => 4830244 [patent_doc_number] => 20080126891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'MEMORY LIFETIME GAUGING SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 11/852129 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126891.pdf [firstpage_image] =>[orig_patent_app_number] => 11852129 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/852129
Memory lifetime gauging system, method and computer program product Sep 6, 2007 Issued
Array ( [id] => 4920831 [patent_doc_number] => 20080069145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'SYSTEM AND METHOD FOR COMMUNICATING DATA OVER COMMUNICATION CHANNELS' [patent_app_type] => utility [patent_app_number] => 11/850702 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10722 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20080069145.pdf [firstpage_image] =>[orig_patent_app_number] => 11850702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850702
System and method for communicating data over communication channels Sep 5, 2007 Issued
Array ( [id] => 9283 [patent_doc_number] => 07814385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Self programmable shared bist for testing multiple memories' [patent_app_type] => utility [patent_app_number] => 11/848107 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3284 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/814/07814385.pdf [firstpage_image] =>[orig_patent_app_number] => 11848107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848107
Self programmable shared bist for testing multiple memories Aug 29, 2007 Issued
Array ( [id] => 87821 [patent_doc_number] => 07743289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/896219 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10104 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743289.pdf [firstpage_image] =>[orig_patent_app_number] => 11896219 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896219
Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit Aug 29, 2007 Issued
Array ( [id] => 4774189 [patent_doc_number] => 20080059851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Semiconductor apparatus and testing method' [patent_app_type] => utility [patent_app_number] => 11/896208 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8150 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059851.pdf [firstpage_image] =>[orig_patent_app_number] => 11896208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896208
Semiconductor apparatus and testing method Aug 29, 2007 Issued
Array ( [id] => 6511276 [patent_doc_number] => 20100011264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'MULTI-CLOCK SYSTEM-ON-CHIP WITH UNIVERSAL CLOCK CONTROL MODULES FOR TRANSITION FAULT TEST AT SPEED MULTI-CORE' [patent_app_type] => utility [patent_app_number] => 12/439394 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3986 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20100011264.pdf [firstpage_image] =>[orig_patent_app_number] => 12439394 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/439394
Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core Aug 28, 2007 Issued
Array ( [id] => 4647029 [patent_doc_number] => 08024642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'System and method for providing constrained transmission and storage in a random access memory' [patent_app_type] => utility [patent_app_number] => 11/846814 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10137 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/024/08024642.pdf [firstpage_image] =>[orig_patent_app_number] => 11846814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846814
System and method for providing constrained transmission and storage in a random access memory Aug 28, 2007 Issued
Array ( [id] => 4472485 [patent_doc_number] => 07937631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Method for self-test and self-repair in a multi-chip package environment' [patent_app_type] => utility [patent_app_number] => 11/846482 [patent_app_country] => US [patent_app_date] => 2007-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4071 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937631.pdf [firstpage_image] =>[orig_patent_app_number] => 11846482 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846482
Method for self-test and self-repair in a multi-chip package environment Aug 27, 2007 Issued
Array ( [id] => 4735589 [patent_doc_number] => 20080052571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Memory test system including semiconductor memory device suitable for testing an on-die termination, and method thereof' [patent_app_type] => utility [patent_app_number] => 11/892846 [patent_app_country] => US [patent_app_date] => 2007-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11501 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052571.pdf [firstpage_image] =>[orig_patent_app_number] => 11892846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892846
Memory test system including semiconductor memory device suitable for testing an on-die termination, and method thereof Aug 27, 2007 Issued
Array ( [id] => 5200792 [patent_doc_number] => 20070300110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Phase shifter with reduced linear dependency' [patent_app_type] => utility [patent_app_number] => 11/895845 [patent_app_country] => US [patent_app_date] => 2007-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9809 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300110.pdf [firstpage_image] =>[orig_patent_app_number] => 11895845 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/895845
Phase shifter with reduced linear dependency Aug 26, 2007 Issued
Array ( [id] => 5339226 [patent_doc_number] => 20090055690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Error catch RAM support using fan-out/fan-in matrix' [patent_app_type] => utility [patent_app_number] => 11/895512 [patent_app_country] => US [patent_app_date] => 2007-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055690.pdf [firstpage_image] =>[orig_patent_app_number] => 11895512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/895512
Error catch RAM support using fan-out/fan-in matrix Aug 23, 2007 Issued
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