Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7689874 [patent_doc_number] => 20070234159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'METHOD AND APPARATUS FOR TESTING A RING OF NON-SCAN LATCHES WITH LOGIC BUILT-IN SELF-TEST' [patent_app_type] => utility [patent_app_number] => 11/278313 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234159.pdf [firstpage_image] =>[orig_patent_app_number] => 11278313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/278313
Method and apparatus for testing a ring of non-scan latches with logic built-in self-test Mar 30, 2006 Issued
Array ( [id] => 309688 [patent_doc_number] => 07533316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Method and apparatus for disabling and swapping cores in a multi-core microprocessor' [patent_app_type] => utility [patent_app_number] => 11/394737 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3172 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533316.pdf [firstpage_image] =>[orig_patent_app_number] => 11394737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394737
Method and apparatus for disabling and swapping cores in a multi-core microprocessor Mar 30, 2006 Issued
Array ( [id] => 5090621 [patent_doc_number] => 20070230260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'AUTOMATIC SHUTDOWN OR THROTTLING OF A BIST STATE MACHINE USING THERMAL FEEDBACK' [patent_app_type] => utility [patent_app_number] => 11/278238 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20070230260.pdf [firstpage_image] =>[orig_patent_app_number] => 11278238 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/278238
Automatic shutdown or throttling of a bist state machine using thermal feedback Mar 30, 2006 Issued
Array ( [id] => 5226724 [patent_doc_number] => 20070255991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'MONITORING A THERMAL PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/278012 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14047 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20070255991.pdf [firstpage_image] =>[orig_patent_app_number] => 11278012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/278012
Monitoring a thermal processing system Mar 29, 2006 Issued
Array ( [id] => 5044920 [patent_doc_number] => 20070263592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method and apparatus for improved routing in connectionless networks' [patent_app_type] => utility [patent_app_number] => 11/394356 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10032 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263592.pdf [firstpage_image] =>[orig_patent_app_number] => 11394356 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394356
Method and apparatus for improved routing in connectionless networks Mar 29, 2006 Issued
Array ( [id] => 829316 [patent_doc_number] => 07404126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs' [patent_app_type] => utility [patent_app_number] => 11/308481 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5704 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404126.pdf [firstpage_image] =>[orig_patent_app_number] => 11308481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308481
Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs Mar 28, 2006 Issued
Array ( [id] => 379137 [patent_doc_number] => 07313746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Test output compaction for responses with unknown values' [patent_app_type] => utility [patent_app_number] => 11/277782 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6727 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313746.pdf [firstpage_image] =>[orig_patent_app_number] => 11277782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/277782
Test output compaction for responses with unknown values Mar 28, 2006 Issued
Array ( [id] => 5928161 [patent_doc_number] => 20060242514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Method and apparatus for generating expect data from a captured bit pattern, and memory device using same' [patent_app_type] => utility [patent_app_number] => 11/393265 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15697 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242514.pdf [firstpage_image] =>[orig_patent_app_number] => 11393265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/393265
Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Mar 28, 2006 Issued
Array ( [id] => 7689888 [patent_doc_number] => 20070234145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Reduced pattern memory in digital test equipment' [patent_app_type] => utility [patent_app_number] => 11/391009 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4154 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234145.pdf [firstpage_image] =>[orig_patent_app_number] => 11391009 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/391009
Reduced pattern memory in digital test equipment Mar 27, 2006 Issued
Array ( [id] => 5064922 [patent_doc_number] => 20070226564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'EFFICIENT SCAN CHAIN INSERTION USING BROADCAST SCAN FOR REDUCED BIT COLLISIONS' [patent_app_type] => utility [patent_app_number] => 11/277375 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226564.pdf [firstpage_image] =>[orig_patent_app_number] => 11277375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/277375
Efficient scan chain insertion using broadcast scan for reduced bit collisions Mar 23, 2006 Issued
Array ( [id] => 5852988 [patent_doc_number] => 20060236179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Delay test method for large-scale integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/384437 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236179.pdf [firstpage_image] =>[orig_patent_app_number] => 11384437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/384437
Delay test method for large-scale integrated circuits Mar 20, 2006 Abandoned
Array ( [id] => 261913 [patent_doc_number] => 07574647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-11 [patent_title] => 'Binary data encoding/decoding such as for communicating between computing platform components over a parallel interconnect' [patent_app_type] => utility [patent_app_number] => 11/385357 [patent_app_country] => US [patent_app_date] => 2006-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5187 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574647.pdf [firstpage_image] =>[orig_patent_app_number] => 11385357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385357
Binary data encoding/decoding such as for communicating between computing platform components over a parallel interconnect Mar 19, 2006 Issued
Array ( [id] => 166815 [patent_doc_number] => 07673219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Cooperative relay networks using rateless codes' [patent_app_type] => utility [patent_app_number] => 11/377711 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3725 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673219.pdf [firstpage_image] =>[orig_patent_app_number] => 11377711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/377711
Cooperative relay networks using rateless codes Mar 15, 2006 Issued
Array ( [id] => 5684444 [patent_doc_number] => 20060200714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Test equipment for semiconductor' [patent_app_type] => utility [patent_app_number] => 11/363948 [patent_app_country] => US [patent_app_date] => 2006-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6421 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200714.pdf [firstpage_image] =>[orig_patent_app_number] => 11363948 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363948
Test equipment for semiconductor Feb 28, 2006 Abandoned
Array ( [id] => 4996214 [patent_doc_number] => 20070011559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Dynamic minimum-memory interleaving' [patent_app_type] => utility [patent_app_number] => 11/363769 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14194 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011559.pdf [firstpage_image] =>[orig_patent_app_number] => 11363769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363769
Dynamic minimum-memory interleaving Feb 27, 2006 Issued
Array ( [id] => 882391 [patent_doc_number] => 07360138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Verification of the design of an integrated circuit background' [patent_app_type] => utility [patent_app_number] => 11/276295 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3890 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360138.pdf [firstpage_image] =>[orig_patent_app_number] => 11276295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/276295
Verification of the design of an integrated circuit background Feb 22, 2006 Issued
Array ( [id] => 261909 [patent_doc_number] => 07574643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Test apparatus and method for testing a circuit unit' [patent_app_type] => utility [patent_app_number] => 11/356713 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3216 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574643.pdf [firstpage_image] =>[orig_patent_app_number] => 11356713 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356713
Test apparatus and method for testing a circuit unit Feb 16, 2006 Issued
Array ( [id] => 5132584 [patent_doc_number] => 20070208981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Systems, devices, and methods for arc fault detection' [patent_app_type] => utility [patent_app_number] => 11/355676 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6781 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20070208981.pdf [firstpage_image] =>[orig_patent_app_number] => 11355676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355676
Systems, devices, and methods for arc fault detection Feb 15, 2006 Issued
Array ( [id] => 5017741 [patent_doc_number] => 20070260950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Method and apparatus for testing a data processing system' [patent_app_type] => utility [patent_app_number] => 11/355681 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9973 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20070260950.pdf [firstpage_image] =>[orig_patent_app_number] => 11355681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355681
Method and apparatus for testing a data processing system Feb 15, 2006 Issued
Array ( [id] => 302196 [patent_doc_number] => 07539926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Method of correcting errors stored in a memory array' [patent_app_type] => utility [patent_app_number] => 11/353740 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539926.pdf [firstpage_image] =>[orig_patent_app_number] => 11353740 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/353740
Method of correcting errors stored in a memory array Feb 13, 2006 Issued
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