Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5696000 [patent_doc_number] => 20060156147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Method and apparatus for measuring group delay of a device under test' [patent_app_type] => utility [patent_app_number] => 11/351734 [patent_app_country] => US [patent_app_date] => 2006-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2635 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156147.pdf [firstpage_image] =>[orig_patent_app_number] => 11351734 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/351734
Method and apparatus for measuring group delay of a device under test Feb 9, 2006 Issued
Array ( [id] => 5852999 [patent_doc_number] => 20060236190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Power control of packet data transmission in cellular network' [patent_app_type] => utility [patent_app_number] => 11/350866 [patent_app_country] => US [patent_app_date] => 2006-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3511 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236190.pdf [firstpage_image] =>[orig_patent_app_number] => 11350866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/350866
Power control of packet data transmission in cellular network Feb 9, 2006 Issued
Array ( [id] => 5706705 [patent_doc_number] => 20060195753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Bitmap manager, method of allocating a bitmap memory, method of generating an acknowledgement between network entities, and network entity implementing the same' [patent_app_type] => utility [patent_app_number] => 11/350910 [patent_app_country] => US [patent_app_date] => 2006-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8447 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195753.pdf [firstpage_image] =>[orig_patent_app_number] => 11350910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/350910
Bitmap manager, method of allocating a bitmap memory, method of generating an acknowledgement between network entities, and network entity implementing the same Feb 9, 2006 Issued
Array ( [id] => 595816 [patent_doc_number] => 07458011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Low complexity hybrid ARQ scheme based on rate compatible zigzag codes' [patent_app_type] => utility [patent_app_number] => 11/350977 [patent_app_country] => US [patent_app_date] => 2006-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8781 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/458/07458011.pdf [firstpage_image] =>[orig_patent_app_number] => 11350977 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/350977
Low complexity hybrid ARQ scheme based on rate compatible zigzag codes Feb 7, 2006 Issued
Array ( [id] => 5052910 [patent_doc_number] => 20070033455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Load testing of a telecommunication network' [patent_app_type] => utility [patent_app_number] => 11/349895 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2476 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20070033455.pdf [firstpage_image] =>[orig_patent_app_number] => 11349895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/349895
Load testing of a telecommunication network Feb 6, 2006 Issued
Array ( [id] => 5017740 [patent_doc_number] => 20070260949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Trading propensity-based clustering of circuit elements in a circuit design' [patent_app_type] => utility [patent_app_number] => 11/348907 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9082 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20070260949.pdf [firstpage_image] =>[orig_patent_app_number] => 11348907 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348907
Trading propensity-based clustering of circuit elements in a circuit design Feb 6, 2006 Issued
Array ( [id] => 5928187 [patent_doc_number] => 20060242538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Multi-bit nonvolatile ferroelectric memory device having fail cell repair circuit and repair method thereof' [patent_app_type] => utility [patent_app_number] => 11/320959 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3847 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242538.pdf [firstpage_image] =>[orig_patent_app_number] => 11320959 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/320959
Multi-bit nonvolatile ferroelectric memory device having fail cell repair circuit and repair method thereof Dec 29, 2005 Issued
Array ( [id] => 5928188 [patent_doc_number] => 20060242539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Nonvolatile ferroelectric memory device including failed cell correcting circuit' [patent_app_type] => utility [patent_app_number] => 11/321869 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5367 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242539.pdf [firstpage_image] =>[orig_patent_app_number] => 11321869 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321869
Nonvolatile ferroelectric memory device including failed cell correcting circuit Dec 29, 2005 Issued
Array ( [id] => 5847125 [patent_doc_number] => 20060123275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior' [patent_app_type] => utility [patent_app_number] => 11/321012 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123275.pdf [firstpage_image] =>[orig_patent_app_number] => 11321012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321012
Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior Dec 27, 2005 Issued
Array ( [id] => 5081405 [patent_doc_number] => 20070124629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Embedded testing circuit for testing a dual port memory' [patent_app_type] => utility [patent_app_number] => 11/291099 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5178 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20070124629.pdf [firstpage_image] =>[orig_patent_app_number] => 11291099 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/291099
Embedded testing circuit for testing a dual port memory Nov 29, 2005 Issued
Array ( [id] => 411500 [patent_doc_number] => 07287201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Data transmission apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/284961 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 8477 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287201.pdf [firstpage_image] =>[orig_patent_app_number] => 11284961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284961
Data transmission apparatus and method Nov 22, 2005 Issued
Array ( [id] => 5099813 [patent_doc_number] => 20070183074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Disk drive defect map encoding scheme' [patent_app_type] => utility [patent_app_number] => 11/286993 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2744 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183074.pdf [firstpage_image] =>[orig_patent_app_number] => 11286993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286993
Disk drive defect map encoding scheme Nov 22, 2005 Abandoned
Array ( [id] => 869002 [patent_doc_number] => 07370263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-06 [patent_title] => 'Hardware efficient CRC generator for high speed communication networks' [patent_app_type] => utility [patent_app_number] => 11/285761 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4963 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/370/07370263.pdf [firstpage_image] =>[orig_patent_app_number] => 11285761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285761
Hardware efficient CRC generator for high speed communication networks Nov 20, 2005 Issued
Array ( [id] => 5695987 [patent_doc_number] => 20060156134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Programmable memory built-in-self-test (MBIST) method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/283527 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 37203 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156134.pdf [firstpage_image] =>[orig_patent_app_number] => 11283527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/283527
Programmable memory built-in-self-test (MBIST) method and apparatus Nov 17, 2005 Issued
Array ( [id] => 605080 [patent_doc_number] => 07434131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Flexible memory built-in-self-test (MBIST) method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/282938 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 40 [patent_no_of_words] => 37257 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434131.pdf [firstpage_image] =>[orig_patent_app_number] => 11282938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/282938
Flexible memory built-in-self-test (MBIST) method and apparatus Nov 17, 2005 Issued
Array ( [id] => 358610 [patent_doc_number] => 07490279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-10 [patent_title] => 'Test interface for random access memory (RAM) built-in self-test (BIST)' [patent_app_type] => utility [patent_app_number] => 11/274664 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2117 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/490/07490279.pdf [firstpage_image] =>[orig_patent_app_number] => 11274664 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274664
Test interface for random access memory (RAM) built-in self-test (BIST) Nov 14, 2005 Issued
Array ( [id] => 691046 [patent_doc_number] => 07080301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'On-chip service processor' [patent_app_type] => utility [patent_app_number] => 11/261762 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 9251 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080301.pdf [firstpage_image] =>[orig_patent_app_number] => 11261762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261762
On-chip service processor Oct 30, 2005 Issued
Array ( [id] => 5778516 [patent_doc_number] => 20060107156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Hub for testing memory and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/260389 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5090 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20060107156.pdf [firstpage_image] =>[orig_patent_app_number] => 11260389 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260389
Hub for testing memory and methods thereof Oct 27, 2005 Issued
Array ( [id] => 840006 [patent_doc_number] => 07395473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Removing the effects of unknown test values from compacted test responses' [patent_app_type] => utility [patent_app_number] => 11/258769 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 17237 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395473.pdf [firstpage_image] =>[orig_patent_app_number] => 11258769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258769
Removing the effects of unknown test values from compacted test responses Oct 24, 2005 Issued
Array ( [id] => 325286 [patent_doc_number] => 07519892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-14 [patent_title] => 'Binary data encoding/decoding with error detection, such as for communicating between computing platform components' [patent_app_type] => utility [patent_app_number] => 11/251405 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3503 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/519/07519892.pdf [firstpage_image] =>[orig_patent_app_number] => 11251405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251405
Binary data encoding/decoding with error detection, such as for communicating between computing platform components Oct 13, 2005 Issued
Menu