
Armand Melendez
Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )
| Most Active Art Unit | 1742 |
| Art Unit(s) | 1742, 1759 |
| Total Applications | 481 |
| Issued Applications | 205 |
| Pending Applications | 93 |
| Abandoned Applications | 214 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6974021
[patent_doc_number] => 20050039097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Systems and methods for scan test access using bond pad test access circuits'
[patent_app_type] => utility
[patent_app_number] => 10/640687
[patent_app_country] => US
[patent_app_date] => 2003-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4828
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20050039097.pdf
[firstpage_image] =>[orig_patent_app_number] => 10640687
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/640687 | Systems and methods for scan test access using bond pad test access circuits | Aug 13, 2003 | Issued |
Array
(
[id] => 6974018
[patent_doc_number] => 20050039094
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Static timing analysis approach for multi-clock domain designs'
[patent_app_type] => utility
[patent_app_number] => 10/639701
[patent_app_country] => US
[patent_app_date] => 2003-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4720
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20050039094.pdf
[firstpage_image] =>[orig_patent_app_number] => 10639701
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639701 | Static timing analysis approach for multi-clock domain designs | Aug 11, 2003 | Issued |
Array
(
[id] => 829291
[patent_doc_number] => 07404112
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-22
[patent_title] => 'Data selection circuit for performance counter'
[patent_app_type] => utility
[patent_app_number] => 10/635103
[patent_app_country] => US
[patent_app_date] => 2003-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4411
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/404/07404112.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635103
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635103 | Data selection circuit for performance counter | Aug 5, 2003 | Issued |
Array
(
[id] => 7036441
[patent_doc_number] => 20050034048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Reliable communication between multi-processor clusters of multi-cluster computer systems'
[patent_app_type] => utility
[patent_app_number] => 10/635793
[patent_app_country] => US
[patent_app_date] => 2003-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 17980
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20050034048.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635793
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635793 | Reliable communication between multi-processor clusters of multi-cluster computer systems | Aug 4, 2003 | Issued |
Array
(
[id] => 671684
[patent_doc_number] => 07096414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-22
[patent_title] => 'In-line wire error correction'
[patent_app_type] => utility
[patent_app_number] => 10/632908
[patent_app_country] => US
[patent_app_date] => 2003-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5234
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/096/07096414.pdf
[firstpage_image] =>[orig_patent_app_number] => 10632908
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/632908 | In-line wire error correction | Aug 3, 2003 | Issued |
Array
(
[id] => 626514
[patent_doc_number] => 07139958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-21
[patent_title] => 'System with interleaver and de-interleaver'
[patent_app_type] => utility
[patent_app_number] => 10/628278
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3629
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/139/07139958.pdf
[firstpage_image] =>[orig_patent_app_number] => 10628278
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628278 | System with interleaver and de-interleaver | Jul 28, 2003 | Issued |
Array
(
[id] => 7235035
[patent_doc_number] => 20040073861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-15
[patent_title] => 'Interleaved reed solomon coding for home networking'
[patent_app_type] => new
[patent_app_number] => 10/628675
[patent_app_country] => US
[patent_app_date] => 2003-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5036
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20040073861.pdf
[firstpage_image] =>[orig_patent_app_number] => 10628675
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628675 | Interleaved reed solomon coding for home networking | Jul 27, 2003 | Abandoned |
Array
(
[id] => 451306
[patent_doc_number] => 07254753
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Circuit and method for configuring CAM array margin test and operation'
[patent_app_type] => utility
[patent_app_number] => 10/626728
[patent_app_country] => US
[patent_app_date] => 2003-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5245
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 22
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/254/07254753.pdf
[firstpage_image] =>[orig_patent_app_number] => 10626728
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/626728 | Circuit and method for configuring CAM array margin test and operation | Jul 24, 2003 | Issued |
Array
(
[id] => 6992523
[patent_doc_number] => 20050091560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'System for optimizing anti-fuse repair time using fuse id'
[patent_app_type] => utility
[patent_app_number] => 10/622496
[patent_app_country] => US
[patent_app_date] => 2003-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2788
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20050091560.pdf
[firstpage_image] =>[orig_patent_app_number] => 10622496
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622496 | System for optimizing anti-fuse repair time using fuse id | Jul 20, 2003 | Issued |
Array
(
[id] => 7262529
[patent_doc_number] => 20040260993
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Method, system, and program for simulating Input/Output (I/O) requests to test a system'
[patent_app_type] => new
[patent_app_number] => 10/465369
[patent_app_country] => US
[patent_app_date] => 2003-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4548
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0260/20040260993.pdf
[firstpage_image] =>[orig_patent_app_number] => 10465369
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/465369 | Method, system, and program for simulating Input/Output (I/O) requests to test a system | Jun 17, 2003 | Issued |
Array
(
[id] => 774318
[patent_doc_number] => 07007208
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-02-28
[patent_title] => 'Systems and methods for data unit modification'
[patent_app_type] => utility
[patent_app_number] => 10/448917
[patent_app_country] => US
[patent_app_date] => 2003-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 17231
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/007/07007208.pdf
[firstpage_image] =>[orig_patent_app_number] => 10448917
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/448917 | Systems and methods for data unit modification | May 29, 2003 | Issued |
Array
(
[id] => 6826411
[patent_doc_number] => 20030237033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'System for testing a group of functionally independent memories and for replacing failing memory words'
[patent_app_type] => new
[patent_app_number] => 10/449580
[patent_app_country] => US
[patent_app_date] => 2003-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7562
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0237/20030237033.pdf
[firstpage_image] =>[orig_patent_app_number] => 10449580
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/449580 | System for testing a group of functionally independent memories and for replacing failing memory words | May 29, 2003 | Issued |
Array
(
[id] => 749640
[patent_doc_number] => 07032149
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-18
[patent_title] => 'Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior'
[patent_app_type] => utility
[patent_app_number] => 10/449332
[patent_app_country] => US
[patent_app_date] => 2003-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3873
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/032/07032149.pdf
[firstpage_image] =>[orig_patent_app_number] => 10449332
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/449332 | Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior | May 29, 2003 | Issued |
Array
(
[id] => 469636
[patent_doc_number] => 07240268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Test component and method of operation thereof'
[patent_app_type] => utility
[patent_app_number] => 10/448331
[patent_app_country] => US
[patent_app_date] => 2003-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 14071
[patent_no_of_claims] => 73
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/240/07240268.pdf
[firstpage_image] =>[orig_patent_app_number] => 10448331
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/448331 | Test component and method of operation thereof | May 29, 2003 | Issued |
Array
(
[id] => 619858
[patent_doc_number] => 07146549
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Scan-path flip-flop circuit for integrated circuit memory'
[patent_app_type] => utility
[patent_app_number] => 10/446122
[patent_app_country] => US
[patent_app_date] => 2003-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2523
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/146/07146549.pdf
[firstpage_image] =>[orig_patent_app_number] => 10446122
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/446122 | Scan-path flip-flop circuit for integrated circuit memory | May 27, 2003 | Issued |
Array
(
[id] => 609630
[patent_doc_number] => 07155652
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-12-26
[patent_title] => 'Digital signal processing for real time classification of failure bitmaps in integrated circuit technology development'
[patent_app_type] => utility
[patent_app_number] => 10/446414
[patent_app_country] => US
[patent_app_date] => 2003-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2690
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/155/07155652.pdf
[firstpage_image] =>[orig_patent_app_number] => 10446414
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/446414 | Digital signal processing for real time classification of failure bitmaps in integrated circuit technology development | May 26, 2003 | Issued |
Array
(
[id] => 777997
[patent_doc_number] => 07003706
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Method, system, and program for improved device blocking and suspension'
[patent_app_type] => utility
[patent_app_number] => 10/445688
[patent_app_country] => US
[patent_app_date] => 2003-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8583
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/003/07003706.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445688
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445688 | Method, system, and program for improved device blocking and suspension | May 26, 2003 | Issued |
Array
(
[id] => 7266794
[patent_doc_number] => 20040243890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory'
[patent_app_type] => new
[patent_app_number] => 10/445437
[patent_app_country] => US
[patent_app_date] => 2003-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2061
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0243/20040243890.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445437
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445437 | Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory | May 26, 2003 | Issued |
Array
(
[id] => 713441
[patent_doc_number] => 07062695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Memory implementation for handling integrated circuit fabrication faults'
[patent_app_type] => utility
[patent_app_number] => 10/444891
[patent_app_country] => US
[patent_app_date] => 2003-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2642
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/062/07062695.pdf
[firstpage_image] =>[orig_patent_app_number] => 10444891
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/444891 | Memory implementation for handling integrated circuit fabrication faults | May 22, 2003 | Issued |
Array
(
[id] => 6703202
[patent_doc_number] => 20030226082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-04
[patent_title] => 'Voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack'
[patent_app_type] => new
[patent_app_number] => 10/443427
[patent_app_country] => US
[patent_app_date] => 2003-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9649
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0226/20030226082.pdf
[firstpage_image] =>[orig_patent_app_number] => 10443427
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/443427 | Voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack | May 21, 2003 | Issued |