Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6784551 [patent_doc_number] => 20030065999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Self-test ram using external synchronous clock' [patent_app_type] => new [patent_app_number] => 10/269623 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4430 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065999.pdf [firstpage_image] =>[orig_patent_app_number] => 10269623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269623
Self-test ram using external synchronous clock Oct 10, 2002 Issued
Array ( [id] => 6793474 [patent_doc_number] => 20030088818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Method and apparatus for generating expect data from a captured bit pattern, and memory device using same' [patent_app_type] => new [patent_app_number] => 10/268351 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15681 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088818.pdf [firstpage_image] =>[orig_patent_app_number] => 10268351 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268351
Method for generating expect data from a captured bit pattern, and memory device using same Oct 8, 2002 Issued
Array ( [id] => 7678196 [patent_doc_number] => 20030196140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/242460 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6710 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196140.pdf [firstpage_image] =>[orig_patent_app_number] => 10242460 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242460
Semiconductor integrated circuit Sep 12, 2002 Abandoned
Array ( [id] => 680281 [patent_doc_number] => 07089467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Asynchronous debug interface' [patent_app_type] => utility [patent_app_number] => 10/225058 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3000 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089467.pdf [firstpage_image] =>[orig_patent_app_number] => 10225058 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225058
Asynchronous debug interface Aug 20, 2002 Issued
Array ( [id] => 1030694 [patent_doc_number] => 06883129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Electronic circuit and method for testing' [patent_app_type] => utility [patent_app_number] => 10/217811 [patent_app_country] => US [patent_app_date] => 2002-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3704 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883129.pdf [firstpage_image] =>[orig_patent_app_number] => 10217811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/217811
Electronic circuit and method for testing Aug 11, 2002 Issued
Array ( [id] => 7394554 [patent_doc_number] => 20040030966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'System, method, and apparatus for detecting and recovering from false synchronization' [patent_app_type] => new [patent_app_number] => 10/217979 [patent_app_country] => US [patent_app_date] => 2002-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030966.pdf [firstpage_image] =>[orig_patent_app_number] => 10217979 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/217979
System, method, and apparatus for detecting and recovering from false synchronization Aug 11, 2002 Issued
Array ( [id] => 7394542 [patent_doc_number] => 20040030965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Method and apparatus for adjusting receiver voltage threshold and phase sampling point using FEC counts' [patent_app_type] => new [patent_app_number] => 10/216243 [patent_app_country] => US [patent_app_date] => 2002-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9885 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030965.pdf [firstpage_image] =>[orig_patent_app_number] => 10216243 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/216243
Method and apparatus for adjusting receiver voltage threshold and phase sampling point using FEC counts Aug 11, 2002 Issued
Array ( [id] => 933498 [patent_doc_number] => 06981185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Methods and apparatus to correct duty cycle' [patent_app_type] => utility [patent_app_number] => 10/215919 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6336 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981185.pdf [firstpage_image] =>[orig_patent_app_number] => 10215919 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215919
Methods and apparatus to correct duty cycle Aug 8, 2002 Issued
Array ( [id] => 7175230 [patent_doc_number] => 20040078710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Method for fault identification in an electrical radial network, an application of the method and an arrangement for fault identification in an electrical radial network' [patent_app_type] => new [patent_app_number] => 10/214447 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 12581 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078710.pdf [firstpage_image] =>[orig_patent_app_number] => 10214447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214447
Method for fault identification in an electrical radial network, an application of the method and an arrangement for fault identification in an electrical radial network Aug 7, 2002 Issued
Array ( [id] => 1030692 [patent_doc_number] => 06883128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'PC and ATE integrated chip test equipment' [patent_app_type] => utility [patent_app_number] => 10/214846 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2646 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883128.pdf [firstpage_image] =>[orig_patent_app_number] => 10214846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214846
PC and ATE integrated chip test equipment Aug 7, 2002 Issued
Array ( [id] => 7618382 [patent_doc_number] => 06944811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Blockage aware zero skew clock routing method' [patent_app_type] => utility [patent_app_number] => 10/215133 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4796 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944811.pdf [firstpage_image] =>[orig_patent_app_number] => 10215133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215133
Blockage aware zero skew clock routing method Aug 6, 2002 Issued
Array ( [id] => 1021030 [patent_doc_number] => 06892334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Method for determining deskew margins in parallel interface receivers' [patent_app_type] => utility [patent_app_number] => 10/214801 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2667 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892334.pdf [firstpage_image] =>[orig_patent_app_number] => 10214801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214801
Method for determining deskew margins in parallel interface receivers Aug 5, 2002 Issued
Array ( [id] => 6784547 [patent_doc_number] => 20030065995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Communication channel accuracy measurement' [patent_app_type] => new [patent_app_number] => 10/214415 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4656 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065995.pdf [firstpage_image] =>[orig_patent_app_number] => 10214415 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214415
Communication channel accuracy measurement Aug 5, 2002 Issued
Array ( [id] => 7618384 [patent_doc_number] => 06944809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Methods of resource optimization in programmable logic devices to reduce test time' [patent_app_type] => utility [patent_app_number] => 10/214025 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3215 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944809.pdf [firstpage_image] =>[orig_patent_app_number] => 10214025 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214025
Methods of resource optimization in programmable logic devices to reduce test time Aug 5, 2002 Issued
Array ( [id] => 7618383 [patent_doc_number] => 06944810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method and apparatus for the testing of input/output drivers of a circuit' [patent_app_type] => utility [patent_app_number] => 10/213728 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4351 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944810.pdf [firstpage_image] =>[orig_patent_app_number] => 10213728 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/213728
Method and apparatus for the testing of input/output drivers of a circuit Aug 5, 2002 Issued
Array ( [id] => 7392061 [patent_doc_number] => 20040022198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Methods and apparatus for simulating random connections' [patent_app_type] => new [patent_app_number] => 10/212608 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5121 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20040022198.pdf [firstpage_image] =>[orig_patent_app_number] => 10212608 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212608
Methods and apparatus for simulating random connections Aug 4, 2002 Abandoned
Array ( [id] => 7474290 [patent_doc_number] => 20040054950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores' [patent_app_type] => new [patent_app_number] => 10/212622 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2912 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054950.pdf [firstpage_image] =>[orig_patent_app_number] => 10212622 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212622
Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores Aug 4, 2002 Issued
Array ( [id] => 992815 [patent_doc_number] => 06920597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Uniform testing of tristate nets in logic BIST' [patent_app_type] => utility [patent_app_number] => 10/209817 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6033 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920597.pdf [firstpage_image] =>[orig_patent_app_number] => 10209817 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/209817
Uniform testing of tristate nets in logic BIST Jul 30, 2002 Issued
Array ( [id] => 6866470 [patent_doc_number] => 20030191996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Scheduling the concurrent testing of multiple cores embedded in an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/210794 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11271 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20030191996.pdf [firstpage_image] =>[orig_patent_app_number] => 10210794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210794
Scheduling the concurrent testing of multiple cores embedded in an integrated circuit Jul 30, 2002 Issued
Array ( [id] => 7413351 [patent_doc_number] => 20040025095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Apparatus and methods for providing enhanced redundancy for an on-die cache' [patent_app_type] => new [patent_app_number] => 10/210342 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9291 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20040025095.pdf [firstpage_image] =>[orig_patent_app_number] => 10210342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210342
Apparatus and methods for providing enhanced redundancy for an on-die cache Jul 30, 2002 Issued
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