Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 290481 [patent_doc_number] => 07549107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-16 [patent_title] => 'Interleaved reed solomon coding for home networking' [patent_app_type] => utility [patent_app_number] => 09/573243 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4964 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/549/07549107.pdf [firstpage_image] =>[orig_patent_app_number] => 09573243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573243
Interleaved reed solomon coding for home networking May 17, 2000 Issued
Array ( [id] => 1424002 [patent_doc_number] => 06539505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method of testing a semiconductor memory, and semiconductor memory with a test device' [patent_app_type] => B1 [patent_app_number] => 09/574702 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4086 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539505.pdf [firstpage_image] =>[orig_patent_app_number] => 09574702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574702
Method of testing a semiconductor memory, and semiconductor memory with a test device May 17, 2000 Issued
Array ( [id] => 1431192 [patent_doc_number] => 06507925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Spatial and temporal alignment of a scan dump for debug of scan-based designs' [patent_app_type] => B1 [patent_app_number] => 09/574710 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1843 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507925.pdf [firstpage_image] =>[orig_patent_app_number] => 09574710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574710
Spatial and temporal alignment of a scan dump for debug of scan-based designs May 17, 2000 Issued
Array ( [id] => 1430674 [patent_doc_number] => 06526539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Turbo decoder' [patent_app_type] => B1 [patent_app_number] => 09/574042 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9118 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526539.pdf [firstpage_image] =>[orig_patent_app_number] => 09574042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574042
Turbo decoder May 17, 2000 Issued
Array ( [id] => 1431613 [patent_doc_number] => 06519734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Single bit error correction, double burst error detection technique' [patent_app_type] => B1 [patent_app_number] => 09/572817 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2483 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519734.pdf [firstpage_image] =>[orig_patent_app_number] => 09572817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572817
Single bit error correction, double burst error detection technique May 16, 2000 Issued
Array ( [id] => 1573862 [patent_doc_number] => 06499118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Redundancy analysis method and apparatus for ATE' [patent_app_type] => B1 [patent_app_number] => 09/574689 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2103 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499118.pdf [firstpage_image] =>[orig_patent_app_number] => 09574689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574689
Redundancy analysis method and apparatus for ATE May 16, 2000 Issued
Array ( [id] => 1410337 [patent_doc_number] => 06557135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Cycling through entirety of error-indicating acknowledgment information' [patent_app_type] => B1 [patent_app_number] => 09/573017 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4135 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557135.pdf [firstpage_image] =>[orig_patent_app_number] => 09573017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573017
Cycling through entirety of error-indicating acknowledgment information May 16, 2000 Issued
Array ( [id] => 1425706 [patent_doc_number] => 06536009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Technique for generating single-bit error-correcting, two-bit burst error-detecting codes' [patent_app_type] => B1 [patent_app_number] => 09/573635 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6910 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/536/06536009.pdf [firstpage_image] =>[orig_patent_app_number] => 09573635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573635
Technique for generating single-bit error-correcting, two-bit burst error-detecting codes May 16, 2000 Issued
Array ( [id] => 1432427 [patent_doc_number] => 06505319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Signal processing circuit and information recording apparatus' [patent_app_type] => B1 [patent_app_number] => 09/573616 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505319.pdf [firstpage_image] =>[orig_patent_app_number] => 09573616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573616
Signal processing circuit and information recording apparatus May 16, 2000 Issued
Array ( [id] => 1357696 [patent_doc_number] => 06591391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method of generating an 8-VSB modulated signal' [patent_app_type] => B1 [patent_app_number] => 09/572697 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1582 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591391.pdf [firstpage_image] =>[orig_patent_app_number] => 09572697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572697
Method of generating an 8-VSB modulated signal May 15, 2000 Issued
Array ( [id] => 1250767 [patent_doc_number] => RE038375 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method and system for the secured distribution of multimedia titles' [patent_app_type] => E1 [patent_app_number] => 09/560334 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8147 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038375.pdf [firstpage_image] =>[orig_patent_app_number] => 09560334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/560334
Method and system for the secured distribution of multimedia titles Apr 26, 2000 Issued
Array ( [id] => 4317079 [patent_doc_number] => 06199188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'System for finding roots of degree three and degree four error locator polynomials over GF(2M)' [patent_app_type] => 1 [patent_app_number] => 9/521518 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8521 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199188.pdf [firstpage_image] =>[orig_patent_app_number] => 521518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521518
System for finding roots of degree three and degree four error locator polynomials over GF(2M) Mar 7, 2000 Issued
Array ( [id] => 1443926 [patent_doc_number] => 06496854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Hybrid memory access protocol in a distributed shared memory computer system' [patent_app_type] => B1 [patent_app_number] => 09/511882 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 12030 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496854.pdf [firstpage_image] =>[orig_patent_app_number] => 09511882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511882
Hybrid memory access protocol in a distributed shared memory computer system Feb 24, 2000 Issued
Array ( [id] => 1472101 [patent_doc_number] => 06460155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Information reproducing system capable of manually reading an optically readable code and repeatedly reproducing voice information included in the code' [patent_app_type] => B1 [patent_app_number] => 09/488244 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 82 [patent_figures_cnt] => 157 [patent_no_of_words] => 46498 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460155.pdf [firstpage_image] =>[orig_patent_app_number] => 09488244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488244
Information reproducing system capable of manually reading an optically readable code and repeatedly reproducing voice information included in the code Jan 19, 2000 Issued
Array ( [id] => 1580509 [patent_doc_number] => 06470465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Parallel test circuit of semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/472608 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8104 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470465.pdf [firstpage_image] =>[orig_patent_app_number] => 09472608 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472608
Parallel test circuit of semiconductor memory device Dec 26, 1999 Issued
Array ( [id] => 1506101 [patent_doc_number] => 06487688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method for testing circuits with tri-state drivers and circuit for use therewith' [patent_app_type] => B1 [patent_app_number] => 09/472386 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6563 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487688.pdf [firstpage_image] =>[orig_patent_app_number] => 09472386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472386
Method for testing circuits with tri-state drivers and circuit for use therewith Dec 22, 1999 Issued
Array ( [id] => 1553172 [patent_doc_number] => 06446227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/471285 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14668 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446227.pdf [firstpage_image] =>[orig_patent_app_number] => 09471285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471285
Semiconductor memory device Dec 22, 1999 Issued
Array ( [id] => 1425628 [patent_doc_number] => 06536002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Buffered redundancy circuits for integrated circuit memory devices' [patent_app_type] => B1 [patent_app_number] => 09/471798 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3566 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/536/06536002.pdf [firstpage_image] =>[orig_patent_app_number] => 09471798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471798
Buffered redundancy circuits for integrated circuit memory devices Dec 22, 1999 Issued
Array ( [id] => 1521863 [patent_doc_number] => 06502216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Memory device testing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/471146 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7951 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502216.pdf [firstpage_image] =>[orig_patent_app_number] => 09471146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471146
Memory device testing apparatus Dec 22, 1999 Issued
Array ( [id] => 1410274 [patent_doc_number] => 06557131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Apparatus and method for automated testing of integrated analog to digital converters' [patent_app_type] => B1 [patent_app_number] => 09/471233 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2572 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557131.pdf [firstpage_image] =>[orig_patent_app_number] => 09471233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471233
Apparatus and method for automated testing of integrated analog to digital converters Dec 22, 1999 Issued
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