Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4334385 [patent_doc_number] => 06243742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Hybrid memory access protocol in a distributed shared memory computer system' [patent_app_type] => 1 [patent_app_number] => 9/236680 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 12001 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243742.pdf [firstpage_image] =>[orig_patent_app_number] => 236680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236680
Hybrid memory access protocol in a distributed shared memory computer system Jan 24, 1999 Issued
Array ( [id] => 4299587 [patent_doc_number] => 06282678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Generic test execution method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/226984 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282678.pdf [firstpage_image] =>[orig_patent_app_number] => 226984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226984
Generic test execution method and apparatus Jan 7, 1999 Issued
Array ( [id] => 1438768 [patent_doc_number] => 06357026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'System and method for at-speed interconnect tests' [patent_app_type] => B1 [patent_app_number] => 09/225950 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1788 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/357/06357026.pdf [firstpage_image] =>[orig_patent_app_number] => 09225950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225950
System and method for at-speed interconnect tests Jan 4, 1999 Issued
09/223184 MEMORY ARRAY ORGANIZATION Dec 29, 1998 Abandoned
Array ( [id] => 1466782 [patent_doc_number] => 06351839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'State metric memory of viterbi decoder and its decoding method' [patent_app_type] => B1 [patent_app_number] => 09/222345 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4585 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351839.pdf [firstpage_image] =>[orig_patent_app_number] => 09222345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222345
State metric memory of viterbi decoder and its decoding method Dec 28, 1998 Issued
Array ( [id] => 1431614 [patent_doc_number] => 06519735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method and apparatus for detecting errors in data output from memory and a device failure in the memory' [patent_app_type] => B1 [patent_app_number] => 09/217814 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2927 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519735.pdf [firstpage_image] =>[orig_patent_app_number] => 09217814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217814
Method and apparatus for detecting errors in data output from memory and a device failure in the memory Dec 21, 1998 Issued
Array ( [id] => 4312920 [patent_doc_number] => 06237116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Testing error correcting code feature in computers that do not have direct hardware features for causing single bit and multi-bit errors' [patent_app_type] => 1 [patent_app_number] => 9/192310 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4173 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237116.pdf [firstpage_image] =>[orig_patent_app_number] => 192310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192310
Testing error correcting code feature in computers that do not have direct hardware features for causing single bit and multi-bit errors Nov 15, 1998 Issued
Array ( [id] => 4274225 [patent_doc_number] => 06209111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Error correction on a mobile device' [patent_app_type] => 1 [patent_app_number] => 9/188755 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8116 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209111.pdf [firstpage_image] =>[orig_patent_app_number] => 188755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188755
Error correction on a mobile device Nov 8, 1998 Issued
Array ( [id] => 4295292 [patent_doc_number] => 06324665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Event based fault diagnosis' [patent_app_type] => 1 [patent_app_number] => 9/185125 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6771 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324665.pdf [firstpage_image] =>[orig_patent_app_number] => 185125 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185125
Event based fault diagnosis Nov 2, 1998 Issued
Array ( [id] => 4085945 [patent_doc_number] => 06009545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'System for analyzing a failure in a semiconductor wafer by calculating correlation coefficient between collated data of defects per prescribed unit and failures per prescribed unit' [patent_app_type] => 1 [patent_app_number] => 9/182526 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 13575 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009545.pdf [firstpage_image] =>[orig_patent_app_number] => 182526 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182526
System for analyzing a failure in a semiconductor wafer by calculating correlation coefficient between collated data of defects per prescribed unit and failures per prescribed unit Oct 29, 1998 Issued
Array ( [id] => 4337859 [patent_doc_number] => 06249893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method and structure for testing embedded cores based system-on-a-chip' [patent_app_type] => 1 [patent_app_number] => 9/183033 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5703 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249893.pdf [firstpage_image] =>[orig_patent_app_number] => 183033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183033
Method and structure for testing embedded cores based system-on-a-chip Oct 29, 1998 Issued
Array ( [id] => 1452472 [patent_doc_number] => 06370664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method and apparatus for partitioning long scan chains in scan based BIST architecture' [patent_app_type] => B1 [patent_app_number] => 09/182543 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2895 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370664.pdf [firstpage_image] =>[orig_patent_app_number] => 09182543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182543
Method and apparatus for partitioning long scan chains in scan based BIST architecture Oct 28, 1998 Issued
Array ( [id] => 4326309 [patent_doc_number] => 06253344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'System and method for testing a microprocessor with an onboard test vector generator' [patent_app_type] => 1 [patent_app_number] => 9/182715 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4390 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253344.pdf [firstpage_image] =>[orig_patent_app_number] => 182715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182715
System and method for testing a microprocessor with an onboard test vector generator Oct 28, 1998 Issued
Array ( [id] => 1425694 [patent_doc_number] => 06536008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Fault insertion method, boundary scan cells, and integrated circuit for use therewith' [patent_app_type] => B1 [patent_app_number] => 09/181077 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 13670 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/536/06536008.pdf [firstpage_image] =>[orig_patent_app_number] => 09181077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181077
Fault insertion method, boundary scan cells, and integrated circuit for use therewith Oct 26, 1998 Issued
Array ( [id] => 4281722 [patent_doc_number] => 06260174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and apparatus for fast-forwarding slave requests in a packet-switched computer system' [patent_app_type] => 1 [patent_app_number] => 9/179048 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10493 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260174.pdf [firstpage_image] =>[orig_patent_app_number] => 179048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179048
Method and apparatus for fast-forwarding slave requests in a packet-switched computer system Oct 25, 1998 Issued
Array ( [id] => 4389120 [patent_doc_number] => 06275962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Remote test module for automatic test equipment' [patent_app_type] => 1 [patent_app_number] => 9/178257 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3275 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275962.pdf [firstpage_image] =>[orig_patent_app_number] => 178257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178257
Remote test module for automatic test equipment Oct 22, 1998 Issued
Array ( [id] => 4295265 [patent_doc_number] => 06324663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'System and method to test internal PCI agents' [patent_app_type] => 1 [patent_app_number] => 9/177789 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5637 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324663.pdf [firstpage_image] =>[orig_patent_app_number] => 177789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177789
System and method to test internal PCI agents Oct 21, 1998 Issued
Array ( [id] => 1466774 [patent_doc_number] => 06351836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Semiconductor device with boundary scanning circuit' [patent_app_type] => B1 [patent_app_number] => 09/176312 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 8311 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351836.pdf [firstpage_image] =>[orig_patent_app_number] => 09176312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176312
Semiconductor device with boundary scanning circuit Oct 21, 1998 Issued
Array ( [id] => 4423058 [patent_doc_number] => 06272656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Semiconductor integrated circuit including test facilitation circuit and test method thereof' [patent_app_type] => 1 [patent_app_number] => 9/172160 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272656.pdf [firstpage_image] =>[orig_patent_app_number] => 172160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172160
Semiconductor integrated circuit including test facilitation circuit and test method thereof Oct 13, 1998 Issued
Array ( [id] => 1553878 [patent_doc_number] => 06347387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links' [patent_app_type] => B1 [patent_app_number] => 09/169848 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6418 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347387.pdf [firstpage_image] =>[orig_patent_app_number] => 09169848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169848
Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links Oct 8, 1998 Issued
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