Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4281684 [patent_doc_number] => 06260172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Semiconductor device with logic rewriting and security protection function' [patent_app_type] => 1 [patent_app_number] => 9/168116 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 22266 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260172.pdf [firstpage_image] =>[orig_patent_app_number] => 168116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/168116
Semiconductor device with logic rewriting and security protection function Oct 7, 1998 Issued
Array ( [id] => 4424342 [patent_doc_number] => 06301678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Test circuit for reducing test time in semiconductor memory device having multiple data input/output terminals' [patent_app_type] => 1 [patent_app_number] => 9/167713 [patent_app_country] => US [patent_app_date] => 1998-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8096 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301678.pdf [firstpage_image] =>[orig_patent_app_number] => 167713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167713
Test circuit for reducing test time in semiconductor memory device having multiple data input/output terminals Oct 6, 1998 Issued
Array ( [id] => 4382151 [patent_doc_number] => 06256765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for checking groups of data formed from a plurality of bytes' [patent_app_type] => 1 [patent_app_number] => 9/163616 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 846 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256765.pdf [firstpage_image] =>[orig_patent_app_number] => 163616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163616
Method for checking groups of data formed from a plurality of bytes Sep 29, 1998 Issued
Array ( [id] => 4374767 [patent_doc_number] => 06292917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Unequal error protection for digital broadcasting using channel classification' [patent_app_type] => 1 [patent_app_number] => 9/163656 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5409 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292917.pdf [firstpage_image] =>[orig_patent_app_number] => 163656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163656
Unequal error protection for digital broadcasting using channel classification Sep 29, 1998 Issued
Array ( [id] => 4402990 [patent_doc_number] => 06279132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Concatenated error control method and system for a processing satellite uplink' [patent_app_type] => 1 [patent_app_number] => 9/161843 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3779 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279132.pdf [firstpage_image] =>[orig_patent_app_number] => 161843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161843
Concatenated error control method and system for a processing satellite uplink Sep 27, 1998 Issued
Array ( [id] => 4299732 [patent_doc_number] => 06282686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Technique for sharing parity over multiple single-error correcting code words' [patent_app_type] => 1 [patent_app_number] => 9/160771 [patent_app_country] => US [patent_app_date] => 1998-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11537 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282686.pdf [firstpage_image] =>[orig_patent_app_number] => 160771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160771
Technique for sharing parity over multiple single-error correcting code words Sep 23, 1998 Issued
Array ( [id] => 4281634 [patent_doc_number] => 06260168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Paging system having optional forward error correcting code transmission at the data link layer' [patent_app_type] => 1 [patent_app_number] => 9/159523 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1504 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260168.pdf [firstpage_image] =>[orig_patent_app_number] => 159523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159523
Paging system having optional forward error correcting code transmission at the data link layer Sep 22, 1998 Issued
Array ( [id] => 4401068 [patent_doc_number] => 06304994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Reed Solomon decoder and decoding method utilizing a control signal indicating a new root for an initial error locator polynomial with respect to new erasure information' [patent_app_type] => 1 [patent_app_number] => 9/154828 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3029 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304994.pdf [firstpage_image] =>[orig_patent_app_number] => 154828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154828
Reed Solomon decoder and decoding method utilizing a control signal indicating a new root for an initial error locator polynomial with respect to new erasure information Sep 16, 1998 Issued
Array ( [id] => 1557418 [patent_doc_number] => 06349399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method and apparatus for generating expect data from a captured bit pattern, and memory device using same' [patent_app_type] => B1 [patent_app_number] => 09/146860 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15695 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349399.pdf [firstpage_image] =>[orig_patent_app_number] => 09146860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146860
Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Sep 2, 1998 Issued
Array ( [id] => 4122819 [patent_doc_number] => 06052813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Dot code including a plurality of blocks wherein each of the blocks has a block address pattern representing an address of each of the blocks' [patent_app_type] => 1 [patent_app_number] => 9/137289 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 82 [patent_figures_cnt] => 154 [patent_no_of_words] => 46116 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052813.pdf [firstpage_image] =>[orig_patent_app_number] => 137289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137289
Dot code including a plurality of blocks wherein each of the blocks has a block address pattern representing an address of each of the blocks Aug 19, 1998 Issued
Array ( [id] => 4404764 [patent_doc_number] => 06263467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Turbo code decoder with modified systematic symbol transition probabilities' [patent_app_type] => 1 [patent_app_number] => 9/137256 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4855 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263467.pdf [firstpage_image] =>[orig_patent_app_number] => 137256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137256
Turbo code decoder with modified systematic symbol transition probabilities Aug 19, 1998 Issued
Array ( [id] => 4127383 [patent_doc_number] => 06058498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Dot code and information recording/reproducing system for recording/reproducing the same' [patent_app_type] => 1 [patent_app_number] => 9/137291 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 82 [patent_figures_cnt] => 154 [patent_no_of_words] => 46103 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058498.pdf [firstpage_image] =>[orig_patent_app_number] => 137291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137291
Dot code and information recording/reproducing system for recording/reproducing the same Aug 19, 1998 Issued
Array ( [id] => 4375232 [patent_doc_number] => 06170077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method for encoding a digital communication channel' [patent_app_type] => 1 [patent_app_number] => 9/135680 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2616 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170077.pdf [firstpage_image] =>[orig_patent_app_number] => 135680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135680
Method for encoding a digital communication channel Aug 17, 1998 Issued
Array ( [id] => 4326351 [patent_doc_number] => 06253347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Automatic synchronization circuit for trellis decoder' [patent_app_type] => 1 [patent_app_number] => 9/135182 [patent_app_country] => US [patent_app_date] => 1998-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5932 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253347.pdf [firstpage_image] =>[orig_patent_app_number] => 135182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135182
Automatic synchronization circuit for trellis decoder Aug 16, 1998 Issued
Array ( [id] => 4261164 [patent_doc_number] => 06167550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Write format for digital data storage' [patent_app_type] => 1 [patent_app_number] => 9/133982 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10080 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167550.pdf [firstpage_image] =>[orig_patent_app_number] => 133982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/133982
Write format for digital data storage Aug 13, 1998 Issued
Array ( [id] => 4347219 [patent_doc_number] => 06330696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Self-testing of DRAMs for multiple faults' [patent_app_type] => 1 [patent_app_number] => 9/128595 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4392 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330696.pdf [firstpage_image] =>[orig_patent_app_number] => 128595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128595
Self-testing of DRAMs for multiple faults Aug 12, 1998 Issued
Array ( [id] => 4403077 [patent_doc_number] => 06279138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'System for changing the parity structure of a raid array' [patent_app_type] => 1 [patent_app_number] => 9/129012 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5243 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279138.pdf [firstpage_image] =>[orig_patent_app_number] => 129012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129012
System for changing the parity structure of a raid array Aug 3, 1998 Issued
Array ( [id] => 4389136 [patent_doc_number] => 06275963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Test circuit and a redundancy circuit for an internal memory circuit' [patent_app_type] => 1 [patent_app_number] => 9/129041 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 47 [patent_no_of_words] => 37766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275963.pdf [firstpage_image] =>[orig_patent_app_number] => 129041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129041
Test circuit and a redundancy circuit for an internal memory circuit Aug 3, 1998 Issued
Array ( [id] => 4261178 [patent_doc_number] => 06167551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'DVD controller with embedded DRAM for ECC-block buffering' [patent_app_type] => 1 [patent_app_number] => 9/124332 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167551.pdf [firstpage_image] =>[orig_patent_app_number] => 124332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124332
DVD controller with embedded DRAM for ECC-block buffering Jul 28, 1998 Issued
Array ( [id] => 4374663 [patent_doc_number] => 06175936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Apparatus for detecting faults in multiple computer memories' [patent_app_type] => 1 [patent_app_number] => 9/118295 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4350 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175936.pdf [firstpage_image] =>[orig_patent_app_number] => 118295 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118295
Apparatus for detecting faults in multiple computer memories Jul 16, 1998 Issued
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