Search

Armand Melendez

Examiner (ID: 2768, Phone: (571)270-0342 , Office: P/1742 )

Most Active Art Unit
1742
Art Unit(s)
1742, 1759
Total Applications
481
Issued Applications
205
Pending Applications
93
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4271236 [patent_doc_number] => 06223323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method for storing parity information in a disk array storage system' [patent_app_type] => 1 [patent_app_number] => 9/118678 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4360 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223323.pdf [firstpage_image] =>[orig_patent_app_number] => 118678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118678
Method for storing parity information in a disk array storage system Jul 16, 1998 Issued
Array ( [id] => 4271135 [patent_doc_number] => 06223316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Vector restoration using accelerated validation and refinement' [patent_app_type] => 1 [patent_app_number] => 9/112945 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10634 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223316.pdf [firstpage_image] =>[orig_patent_app_number] => 112945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112945
Vector restoration using accelerated validation and refinement Jul 9, 1998 Issued
Array ( [id] => 4115214 [patent_doc_number] => 06049899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Soft errors handling in EEPROM devices' [patent_app_type] => 1 [patent_app_number] => 9/113800 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7629 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049899.pdf [firstpage_image] =>[orig_patent_app_number] => 113800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113800
Soft errors handling in EEPROM devices Jul 7, 1998 Issued
Array ( [id] => 4271123 [patent_doc_number] => 06223315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'IP core design supporting user-added scan register option' [patent_app_type] => 1 [patent_app_number] => 9/107105 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3368 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223315.pdf [firstpage_image] =>[orig_patent_app_number] => 107105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107105
IP core design supporting user-added scan register option Jun 29, 1998 Issued
Array ( [id] => 4377424 [patent_doc_number] => 06219813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip' [patent_app_type] => 1 [patent_app_number] => 9/106959 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6089 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219813.pdf [firstpage_image] =>[orig_patent_app_number] => 106959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106959
Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip Jun 28, 1998 Issued
Array ( [id] => 6245546 [patent_doc_number] => 20020046382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'METHOD AND APPARATUS FOR DETECTING AND CORRECTING ERRORS USING CYCLIC REDUNDANCY CHECK' [patent_app_type] => new [patent_app_number] => 09/103421 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9956 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046382.pdf [firstpage_image] =>[orig_patent_app_number] => 09103421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103421
Method and apparatus for detecting and correcting errors using cyclic redundancy check Jun 23, 1998 Issued
Array ( [id] => 4177460 [patent_doc_number] => 06158037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Memory tester' [patent_app_type] => 1 [patent_app_number] => 9/091606 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5283 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158037.pdf [firstpage_image] =>[orig_patent_app_number] => 091606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/091606
Memory tester Jun 18, 1998 Issued
Array ( [id] => 7642327 [patent_doc_number] => 06430719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'General port capable of implementing the JTAG protocol' [patent_app_type] => B1 [patent_app_number] => 09/097022 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430719.pdf [firstpage_image] =>[orig_patent_app_number] => 09097022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097022
General port capable of implementing the JTAG protocol Jun 11, 1998 Issued
Array ( [id] => 4254597 [patent_doc_number] => 06119175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'On-chip communication circuit and protocol for microcontroller-based ASICs' [patent_app_type] => 1 [patent_app_number] => 9/093531 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2685 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119175.pdf [firstpage_image] =>[orig_patent_app_number] => 093531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093531
On-chip communication circuit and protocol for microcontroller-based ASICs Jun 7, 1998 Issued
Array ( [id] => 4318617 [patent_doc_number] => 06185714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Address trap comparator capable of carrying out high speed fault detecting test' [patent_app_type] => 1 [patent_app_number] => 9/092087 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4311 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185714.pdf [firstpage_image] =>[orig_patent_app_number] => 092087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092087
Address trap comparator capable of carrying out high speed fault detecting test Jun 4, 1998 Issued
Array ( [id] => 4118737 [patent_doc_number] => 06098186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Test permutator' [patent_app_type] => 1 [patent_app_number] => 9/087780 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2911 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098186.pdf [firstpage_image] =>[orig_patent_app_number] => 087780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087780
Test permutator May 28, 1998 Issued
Array ( [id] => 4400997 [patent_doc_number] => 06304990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Error correction and concealment technique' [patent_app_type] => 1 [patent_app_number] => 9/084121 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 9123 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304990.pdf [firstpage_image] =>[orig_patent_app_number] => 084121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084121
Error correction and concealment technique May 25, 1998 Issued
Array ( [id] => 4269879 [patent_doc_number] => 06138262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Memory address generator in convolutional interleaver/deinterleaver' [patent_app_type] => 1 [patent_app_number] => 9/083192 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2185 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138262.pdf [firstpage_image] =>[orig_patent_app_number] => 083192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083192
Memory address generator in convolutional interleaver/deinterleaver May 21, 1998 Issued
Array ( [id] => 4350412 [patent_doc_number] => 06321354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Testable circuit with a low number of leads' [patent_app_type] => 1 [patent_app_number] => 9/067893 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321354.pdf [firstpage_image] =>[orig_patent_app_number] => 067893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067893
Testable circuit with a low number of leads Apr 27, 1998 Issued
Array ( [id] => 4425024 [patent_doc_number] => 06230296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method and apparatus for providing error correction' [patent_app_type] => 1 [patent_app_number] => 9/063342 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5183 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230296.pdf [firstpage_image] =>[orig_patent_app_number] => 063342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063342
Method and apparatus for providing error correction Apr 19, 1998 Issued
Array ( [id] => 4336016 [patent_doc_number] => 06243846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Forward error correction system for packet based data and real time media, using cross-wise parity calculation' [patent_app_type] => 1 [patent_app_number] => 9/062435 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9603 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243846.pdf [firstpage_image] =>[orig_patent_app_number] => 062435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062435
Forward error correction system for packet based data and real time media, using cross-wise parity calculation Apr 16, 1998 Issued
Array ( [id] => 4281648 [patent_doc_number] => 06260169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Device and method for real time correction of row data from DVD media' [patent_app_type] => 1 [patent_app_number] => 9/052917 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6319 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260169.pdf [firstpage_image] =>[orig_patent_app_number] => 052917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052917
Device and method for real time correction of row data from DVD media Mar 30, 1998 Issued
Array ( [id] => 4261081 [patent_doc_number] => 06167545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Self-adaptive test program' [patent_app_type] => 1 [patent_app_number] => 9/044585 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2865 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167545.pdf [firstpage_image] =>[orig_patent_app_number] => 044585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044585
Self-adaptive test program Mar 18, 1998 Issued
Array ( [id] => 4424548 [patent_doc_number] => 06266749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Access time measurement circuit and method' [patent_app_type] => 1 [patent_app_number] => 9/041264 [patent_app_country] => US [patent_app_date] => 1998-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 3960 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266749.pdf [firstpage_image] =>[orig_patent_app_number] => 041264 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/041264
Access time measurement circuit and method Mar 11, 1998 Issued
Array ( [id] => 4404752 [patent_doc_number] => 06263466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'System and method of separately coding the header and payload of a data packet for use in satellite data communication' [patent_app_type] => 1 [patent_app_number] => 9/035645 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8227 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263466.pdf [firstpage_image] =>[orig_patent_app_number] => 035645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035645
System and method of separately coding the header and payload of a data packet for use in satellite data communication Mar 4, 1998 Issued
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